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FPGA implementation

of a first order 2-D IIR


beam filter
Guided By,
Dr. Manju
Manuel

SIJI P V
AECE
No:16

INTRODUCTION
Signals emitted from sources far away from the
receiver can be approximated as spatio temporal plane
waves (STPW) at the receiver.
Beamforming
Highly selective enhancement of desired STPWs
according to their directions of arrival (DOA).
Spatio-temporal plane wave filters are used .

Has applications in wireless communications,


biomedical imaging, seismic signal processors,
directional audio systems.

Spatio-temporal plane wave filters


2-D IIR beam filter
Can be realized using a first-order resistively terminated
passive prototype 2-D network.

CONTND..
(i) 2-D s-domain transfer function

2-D frequency response transfer function

2-D z-domain transfer function

CONTND..
(iv) Magnitude frequency response

2-D InputOutput Difference Equation

Filter Architecture
The 2-D space-time input-output direct form difference
equation is used for real-time hardware implementation.
Hardware implementation : Systolic array architecture
Why systolic array architecture?
High-speed plane-wave filtering requires a throughput of
one frame per clock cycle (OFPCC) and very low critical
path (CP) delays for fast real-time operation.
Systolic array architecture has a throughput of One
Frame Per Clock Cycle much lower critical path delay .

CONTND..
(i) Overview of the architecture
()consists of an array of identical parallel processing
core-modules ( PPCMs).
()Each PPCM is capable of producing an output sample
in one clock cycle, therefore leading to a total
throughput of OFPCC.

CONTND..
PPCM hardware architecture

Systolic Array Architecture

REAL TIME
IMPLEMENTATION
Device to be used: Xilinx Virtex 5 XC5VFX70T1FFG1136 (ML507) FPGA device.
FPGA design tool - Xilinx System Generator (XSG)
Verification
The correct operation of the 2D IIR filter is verified
by exciting the inputs of the filter by a 2-D unit
impulse function and measuring the impulse response
from the onchip realizations

DESIGN FLOW

PROPOSALS
Hardware realization of first order 2-D IIR beam
filter on Xilinx Virtex 5 XC5VFX70T-1FFG1136
(ML507)FPGA device .
Computational complexity reduction by representing
multipliers in Signed Power of Two (SPT) space.

CONCLUSION
Systolic implementation of a 2-D IIR frequency beam
filter transfer function has promising engineering
applications for the directional enhancement of a
propagating broadband space-time plane wave
received on an array of sensors.
Systolic array architecture is capable of processing
one frame per clock cycle(OFPCC) and has low CP
(enables high- speed real-time operation).

REFERENCES
A. Madanayake and L. T. Bruton, A speed-optimized systolic
array processor architecture for spatio-temporal 2-D IIR
broadband beam filters, IEEE Trans. Circuits Syst. I, Reg
Papers, vol. 55, no. 7, pp. 19531966, Aug. 2008.
M. Ghavami and R. Kohno, Frequency selective broadband
beamforming using 2-D digital filters, in Proc. IEEE 200 Veh.
Tech. Conf. (VTC00), 2000, pp. 25222526.
M. A. Sid-Ahmed, A systolic realization for 2-D digital filters,
IEEE Trans. Acoust., Speech, Signal Process., vol. 37, no. , pp.
560565, Apr.1989.

THANK YOU

Progress Report
Simulated a simple low pass filter using filter
builder tool and generated verilog code.
Familiarized Xilinx system generator (XSG)tool.
Generated MATLAB code for 2-D IIR beam filter
and plotted magnitude response of the filter.
Designed PPCM block using XSG tool.

Contnd.

CONTD..