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Memory testing
1. Motivation for testing memories (4)
2. Modeling memory chips (6)
3. Reduced functional fault models (17)
4. Traditional tests (7)
5. March tests (7)
6. Pseudorandom memory tests (10)
% of chip area
90%
80%
70%
60%
50%
40%
30%
20%
10%
Memory
Logic-Reused
Logic-New
0%
99
02
05
08
11
14
year
0.001 s
2.1 s
9.2 s
40.3 s
174 s
2.09 h
8.94 h
0.003 s
110 s
860 s
1.91 h
15.3 h
122 h
977 h
0.1 s
30.6 h
20.3 d
325 d
14.2 y
228 y
3655 y
Consequence
More complex fault behavior
More global fault behavior (ground bounce, coupling effects)
Result: Number of bits to be tested increases exponentially, fault
behavior becomes more complex, while test cost has to be same
Q1--Q3 and Q2--Q4 form inverters (Q3 and Q4 are the load devices)
Inverters are cross coupled to form a latch
Q5 and Q6 are pass transistors
Operations
CMOS
Q3
Q4
Q5
Q1
Q6
SRAM
Cell
BL
Q2
VSS
BL
VDD
SRAM
Cell with
WL
Polysilicon
L1 L2
Q6
Q5
Q1
Load
Devices
L1 and L2 BL
WL
Q2
VSS
BL
WL
Operations
Read: precharge BL; drive WL;
feed BL to sense amplifier
Write: drive BL; drive WL
BL
Vcc
Cell capacitor
2.4 Decoders
Decoders address a specific cell in the Memory Cell Array MCA
If the MCA would be a vector, then 1 Mbit MCA requires 1M WLs
By arranging the cells in the MCA in a two-dimensional structure,
a 1 Mbit MCA requires 1K WLs and 1 K BLs
This is a significant reduction in the decoder area!
Hence, the MCA is two dimensional and consists of rows and columns
The Column decoder selects a particular Column
The Row decoder selects a particular Row
Example of a
simple k-input
decoder
a simple inverter; e.g. for small arrays, which have strong signals
a differential amplifier; for larger arrays, which have weak signals
a hierarchy:
1. Stuck-at fault (SAF)
2. Transition fault (TF)
3a. Coupling fault (CF)
3b. Neighborhood pattern
sensitive fault (NPSF)
Address
Address decoder
Memory cell array
Read/write logic
Data
</0>: an TF
</1>: a TF
<;0>: a CFid
<;1>: a CFid
<;0>: a CFid
<;1>: a CFid
/
2-cell fault
<S;F>
0: a SA0 fault
1: a SA1 fault
w0
w1
S0
w0
w1
S0
w1
SA0 fault
w0
Good cell
S1
w0
w1
S1
SA1 fault
VDD
L1 L2
WL
Q6
Q5
Q1
BL
Q2
VSS
SOpF
BL
w0
w1
Cell with
w1
S0
w0
S1
</0> TF
Defect
Conceptual TF
representation
S
R
Cell
Q
Q*
DRF
Q6
Q5
Q1
BL
WL
Q2
VSS
BL
<;0>
A
v-cell
<;0>
v-cell
B
a-cell
e
v
e
NPSF
a
v
e
e
a
v
e
CFid
e
e
e
TF
a
v
e
v
e
CFst
Probability
R-defect
21.0%
0%
9.9%
0%
17.8%
100%
11.9%
7.0%
13.2%
3.3%
14.8%
100%
Case a:
Case b:
a1 v1
a2
Case e:
a1 v1 v2
Case d:
a1
a2
v1
a2
v2
v2
Case c:
a1
v2
v1
a2
Case f:
a
Case b: <;1>
Case a:
<;1>
a1
v1
<;0>
a2
v2
<;0>
a1
a2
v1=v2
Ax
Cx
Fault A
Reading
from
address Ay
Cx Ax
Cx
Ax
Cx
Ay
Fault B
Cy Ay
Fault C
Cy
Ay
Fault D
Cy
Ax
Cx=1
Ax
Cx=0
Ay
Cy=1
Ay
Cy=1
Ax
x2
w2
b2
y2
z2
x1
b1
z1
Address
Address decoder
Memory cell array
Read/write logic
Data
Ax
Fault A
Cx
Ax
Ay
Fault B
Cx Ax
Cx
Ax
Cx
Cy Ay
Fault C
Cy
Ay
Fault D
Cy
Ax
Cx
Ay
Cy
Original
Fault D
Av
Aw
Cv
Cw
Ax
Ay
Az
Cx
Cy
Cz
Fault D1
Ax
Ay
Az
Av
Fault Aw
Ax
D3
Cx
Cy Fault
Cz D2
Cv
Cw
Cx
Fault coverage
of MATS+
</0>
TFs
AFs, SAFs
Rows
Columns
Row
stripe
000000
111111
000000
111111
Checker 010101
board 101010
010101
101010
4.5 Checkerboard
Is SCAN test, using checkerboard data background pattern
Step 1:
Step 2:
Step 3:
w1 in all cells-W
B W B W
w0 in all cells-B
W B W B
B W B W
W B W B
w1 in all cells-B
Step1 pattern
Checkerboard
Step 4: read all cells
data background
Test length: 4*2N operations; which is O(n)
Fault detection capability:
Condition AF not satisfied : 1. (rx,,wx*); 2. (rx*,,wx)
If address decoder maps all cells-W to one cell, and all cells-B to another
cell, then only 2 cells guaranteed fault free
Walking 1/0
Base
cell
GALPAT
GALROW
March C Detects AFs, SAFs, TFs, and unlinked CFins, CFsts, CFids
March A
Detects AFs, SAFs, TFs, CFins, CFsts, CFids, linked CFids (but not
linked with TFs)
March B
Detects AFs, SAFs, TFs, CFins, CFsts, CFids, linked CFids
5.2 MATS+
MATS+ algorithm: {(w0);(r0,w1);(r1,w0)}
Fault coverage
AFs detected because MATS+ satisfies Cond. AF
(When reads, accessing multiple cells, return a random value)
Cond. AF: 1. (rx,,wx*) and 2. (rx*,,wx)
(1) satisfied by: (r0,w1) and (2) by: (r1,w0)
SAFs are detected: from each cell the value 0 and 1 is read
Test length: 5*n
{(w0);(r0,w1);(r1,w0)} {(w1);(r1,w0);(r0,w1)}
s s:
{(w0);(r0,w1);(r1,w0)} {(w0);(r0,w1);(r1,w0)}
0s1s,ss:
{(w1);(r1,w0);(r0,w1)}{(w1);(r1,w0);(r0,w1)}
5.3 March C-
Case 1a
a1
Linked
fault
<;1>
<;0>
a2 a1
Fault subtype
a. CFid <;0>; b. CFid <;1>; c. CFid <;0>; d. CFid<;1>
WL
Q6
Q2
BL
VDD
L1 L2
DRF
Q6
Q5
Q1
BL
WL
Q2
VSS
BL
Purpose
Sources of material
Mazumder, P. and Patel, J.H. (1992). An Efficient Design of Embedded Memories and
their Testability Analysis using Markov Chains. JETTA, Vol. 3, No. 3; pp. 235-250
Krasniewski, A. and Krzysztof, G. (1993). Is There Any Future for Deterministic SelfTest of Embedded RAMs? In Proc. ETC93; pp. 159-168
van de Goor, A.J. (1998). Testing Semiconductor Memories, Theory and Practice.
ComTex Publishing, Gouda, The Netherlands
van de Goor, A.J. and de Neef, J. (1999). Industrial Evaluation of DRAM Tests. In Proc.
Design and Test in Europe (DATe99), March 8-13, Munich; pp. 623-630
van de Goor, A.J. and Lin, Mike (1997). The Implementation of Pseudo-Random Tests
on Commercial Memory Testers. In Proc. IEEE Int. Test Conf., Washington DC, 1997,
pp. 226-235
Reference data
Reference
signature
Compara
tor
Address N RAM
under
lines
R/W line
test
1
B
Data
Memory size
n=32 n=1k n=32k n=1024k
0.1
17
17
17
17
0.01
33
33
33
33
0.001
48
48
48
48
0.0001
64
64
64
64
0.00001 80
80
80
80
v
e
Test
k pG
pa=pd=pw=0.5; e=0.001
DADWRD RARWRD
2 1
90
228
3 pd
202
449
4 p d2
424
891
5 p d3
866
1775
Note: k= Neigborhood Size
Observations
Number of operations roughly doubles if k increases by 1
SAF
CFid
ANPSF k=3
APSF k=3
ANPSF k=5
APSF k=5
Observations
Note: ANPSFs have k-2 cells in only one position
For simple fault models deterministic tests more efficient
- Detect all faults of some fault models with e = 0
For complex fault models PR tests do exist
- PR tests detect all faults of all fault models, however with e > 0
Pseudo-random tests
Not targeted towards a particular fault model
PR tests detect faults of all fault models; however, with some e > 0
Long test time: Test length (TL) proportional to ln(e) and 2k-2
For CFids: 445*n (e = 10-5) versus 10*n (for March C-)
Less of a problem for SRAMs (e.g.,1 Mwrd, 1ns, 1000n test takes1s)
Random pattern resistant faults
with a large data state (e.g., bit line imbalance)
requiring a large address/operation state (e.g., Hammer tests)
Cannot locate faults easily (For laser/dynamic repair)
Well suited for BIST
Very useful for verification purposes
Used for production SRAM testing (together with deterministic tests)
Unknown fault models, short time to volume, high speed SRAM