Issues

Multiple clock domains

Multiple frequencies
Clock skew between clock domains
On-chip PLL generated clocks
Multiple PLLs for deskewing
Invalidation of delay tests
Overtesting (testing of sequential false paths)
Design of scan enable signals
Power dissipation
Ground bounce

Objectives
Apply test with system timing in the capture window

Clk1

Clk2

Clk3

Multiple frequencies
F1

F2

F3
Capture domain
Launch domain

F1
F1
F2
F3

F2

F3

Multiple clock domains

D1

D2

D3
Capture domain
Launch domain

D1
D1
D2
D3

D2

D3

Single clock domain, single capture

last shift

capture

loading

unloading

Clk
shift mode

Sen
capture mode

Capture window: from last shift to capture

Scan enable has to propagate to all scan cells in
less than one cycle
Overtesting - transitions may be launched from an
illegal state
Delay test may be invalidated

Scan enable signal for at-speed scan

Scan enable signal designed as a clock tree

clock
scan enable

Pipelined scan enable signal

clock
scan enable

Speed of loading
S

Clock
suppression

Clock
suppression

Only the timing in capture window is crucial to

at-speed testing
The loading and unloading frequency is
irrelevant to at-speed testing
Slower frequency can be used to reduce power
and constraints on test controller
Faster frequency can be used to reduce the test
application time

Double capture

Launch from a semi-legal state

Reduced overtesting
Double time frame sequential fault simulation

Time
frame
1

last shift

Clk
Sen

Time
frame
2
first capture & transition launch
capture

Slow scan enable

Scan enable
signal has 1.5
cycle to
propagate

clock
scan enable

last shift

Clk
Sen

capture capture
Clock
suppression

first shift
Clock
suppression

Slow scan enable

last shift

Clk

launch capture
Clock
suppression

Sen

Loading of random state

first shift
Clock
suppression

Slow scan enable

last shift

Clk

launch capture
Clock
suppression

first shift
Clock
suppression

Sen

1. Initialization of internal nodes

2. Deactivation of scan enable
3. Propagation of scan enable signal (1.5 cycle)
4. Transition to a semi-legal state
5. Launch of transitions

Slow scan enable

last shift

Clk

launch capture
Clock
suppression

first shift
Clock
suppression

Sen

1. Propagation of signals
2. Capture of responses

Slow scan enable

last shift

Clk

launch capture
Clock
suppression

first shift
Clock
suppression

Sen

1. Activation of scan enable

2. Propagation of scan enable
3. First shift out of responses

Slow scan enable

last shift

Clk

launch capture
Clock
suppression

first shift
Clock
suppression

Sen

Continued unloading of responses

Phase lock loop circuit

Frequency synthesis

Clock

PLL
PLL

ffpp// nn

fp = nfclk

PLL deskewing
PLL
PLL11
Clock

PLL
PLL22

Deskewing
No

Yes
global skew

Clock skew and race conditions

clock

Clock skew results in race

Separate capture required

Fundamental principle
If clock skew is not managed between A and B
If there is logic driven by A and captured in B
There should be no simultaneous change of
state in A and capture in B

Domain A

Shift or capture

Domain B

Capture

Multiple clock domains

Objective: at-speed testing of logic within every
clock domain and between clock domains
BIST mode

SE
CLK
SE
CLK
SE
CLK

PLL
PLL
Test mode

Implementation - clock suppressed

D1
D2
D3

Clock
suppression

Clock
suppression

S*

Clock
suppression

S*

Clock
suppression

S*

Clock
suppression

Clock
suppression

Robust operations assured with clock skew between domains

Captured and shifted data used as a stimuli for other domains
The order of capture can change in different vectors
Combinational fault simulation is sufficient as the response
data is shifted out

One scan enable signal can be used for all domains

Implementation with hold states

SE

Control
Control

scan
CLK

D1

S*

S*

D2

S*

D3

Clock suppression replaced with hold state

Non-capturing domains put in hold state

Multiple frequencies - single capture

Load / unload window

Capture window

Clk1
Clk1*

Sen1
Clk2*

Sen2

All intra and inter domain logic is tested at speed

Combinational fault simulation is adequate

Slow enable and multiple frequencies

Clk1

Clk1*
Sen1
Clk2*
Sen2

Multiple clock domains

D1

D2

D3

S
C

S
S

Multiple clocks per capture cycle

All inter domain logic can be tested
Sequential fault simulation

C
C

Multiple clock domains domain analysis

D1

D2

D3

C
C
C

C
C

Merging non-interacting clock domains

Allows several clocks to be targeted at once

Reduces tester clock requirements

More efficient patterns
Better pattern count

Clock routing
clock signals feeding BIST ready netlist

Control

Sout

Sen
Scan
Scan

Sen

...

P
R
P
G

...

Clock

Sin

BIST
clock

Scan
Scan

PLL
PLL
Shift
Shift counter
counter
BIST Run
External clock
source

Pattern
Pattern counter
counter
BIST Reset

hold

BIST
Done

M
I
S
R

Embedded clock control

clk1 - fastest PLL output

Inputs
from PLL

Capture waveform
generator for clk1

clk1 - out

Capture waveform
generator for clk2

clk2 - out

clk3 - out

Capture waveform
generator for clk3

Shift clock generator

(Clock divider)

Capture window

BIST Run
BIST clock

Summary

Handling of multiple frequency and clock domains

Handling of very high speed designs with on-chip
clocks
At-speed test in every inter- and intra-clock domain
Robust handling of clock skews through clock
suppression and hold state
Separation of timing in loading-unloading and capture
No simultaneous change of state and capture in
interacting domains without skew management
At-speed test is possible without at-speed scan
Power and ground bouncing can be managed by clock
suppression and staggering in shift