RESETS

CONTENTS
WHY RESET ?
TWO TYPES OF RESETS
SYNCHRONOUS RESET
SYNCHRONOUS RESETS: PROS AND CONS
ASYNCHRONOUS RESET
ASYNCHRONOUS RESETS: PROS AND CONS
DEASSERTION OF ASYNCHRONOUS RESET: AN ISSUE
DEASSERTION OF ASYNCHRONOUS RESET: SOLUTION 1 -> USE RESET SYNCHRONIZERS
DEASSERTION OF ASYNCHRONOUS RESET: BEST SOLUTION -> ASYNCHRONOUS ASSERTION,
SYNCHRONOUS DE-ASSERTION
RESET GLITCH FILTERING: A SOLUTION FOR GLITCHES IN ASYNCHRONOUS RESETS
CONCLUSION
REFERENCES

WHY RESET ?
Reset is needed for:
forcing the ASIC into a known state for simulation
initializing hardware, as circuits have no way to self-initialize
Reset is usually applied at the beginning of time for simulation
Reset is usually applied during power-up for real hardware

TWO TYPES OF RESETS

Synchronous Reset
Reset signal will only affect or reset the state of the flip-flop on the active edge
of a clock.
Asynchronous Reset
Affects or resets the state of the flip-flop asynchronously i.e. no matter what the
clock signal is.

SYNCHRONOUS RESET

SYNCHRONOUS RESETS: PROS & CONS

PROS
Reset presented to all functional flip-flops is fully synchronous to the clock and will
always meet the reset recovery time.
Synchronous reset logic will synthesize to smaller flip-flops.
Glitch in the reset wouldnt be sensed (unless it occurs at clock edge).
CONS
May require a Pulse Stretcher to guarantee a reset pulse is wide enough to be
sampled at clock edge.
In low power designs, if clock is gated, these synchronous resets wont work.
Faster designs cannot afford to have delays in data path caused by adding logic to
handle synchronous resets.

ASYNCHRONOUS RESET

ASYNCHRONOUS RESETS: PROS & CONS

PROS

Circuit can be reset with or without a clock present.

Data path is independent of reset signal

High speeds can be achieved

CONS

Major Disadvantage is Deassertion of reset during Reset Recovery or Removal

time window

If reset is released at or near the active clock edge of a flip-flop, the output of the
flip-flop could go metastable.

Spurious resets can happen due to reset signal glitches.

DEASSERTION OF ASYNCHRONOUS RESET: AN ISSUE

DEASSERTION OF ASYNCHRONOUS RESET: SOLUTION 1 -> USE RESET SYNCHRONIZERS

Guideline: EVERY ASIC USING AN ASYNCHRONOUS

RESET SHOULD INCLUDE A RESET
SYNCHRONIZER CIRCUIT!!

DEASSERTION OF ASYNCHRONOUS RESET: BEST SOLUTION ->

ASYNCHRONOUS ASSERTION, SYNCHRONOUS DE-ASSERTION

RESET GLITCH FILTERING: A SOLUTION FOR GLITCHES IN

ASYNCHRONOUS RESETS

CONCLUSION
Using asynchronous resets is the surest way to guarantee reliable reset assertion.
Removal of an asynchronous reset can cause significant problems if not done properly.
The proper way to design with asynchronous resets is use of Asynchronous assertion, synchronous deassertion approach to ensure normal design functionality.

THANK YOU !!!