Professional Documents
Culture Documents
Wen-Hung Liao,
Ph.D.
Objectives
Transition Present
State
Next State
00
01
10
11
Design Procedure
Step1:
Example
MOD-5
synchronous
counter
000001010011
100000
State transition diagram
K-maps
JA=C,
Final Implementation
Final Implementation
Shift-Register Counters
Use
Counter
Does not require decoding gates
Johnson Counter
Also
Counter Applications
Frequency
Timing Diagram
Digital Clock
HOURS Section
Integrated-Circuit Registers
Parallel