Digital System Design Using Verilog HDL

Digital System
Design
Using
Verilog
Reference: Verilog HDL by Samir Palnitkar
By:
Vimal Kant Pandey
By: Vimal Kant Pandey
Digital System Design
Using Verilog
Design Flow
Design
Specification
Gate Level
Netlist
Behavioral
Description
Logical
Verification
& Testing
RTL
Description
Floor
Planning
Automatic
Place &
Route
Functional
Verification
&
Testing
Logic
Synthesis
Physical
Layout
Layout
Verification
Implementatio
n

Using Verilog
Design Methodologies
There are two basic approaches to

design digital systems:
Top-down approach
Bottom-up approach

Using Verilog
Top Down Methodology

Top Level Block
Subblock1
Leaf
cell
Leaf
cell
Subblock n
Sub-block
2
Leaf
cell
Leaf
cell
Leaf
cell

Using Verilog
Leaf
cell
Bottom-Up Methodology
Top Level Block
MacroCell 1
Leaf
cell
Leaf
cell
MacroCell
2
Leaf
cell
MacroCell n
Leaf
cell
Leaf
cell

Using Verilog
Leaf
cell
Basic Conventions
Verilog is case sensitive

Keywords are in lowercase
Extra white space is ignored
But whitespace does separate tokens
Comments
One liners are //
Multiple lines /* */
Comments may not be nested
Using Verilog
Module- Basic Building Block

Syntax
module <module_name>
(module_terminal_list);
.
.
<module_internals>
endmodule
Example
module T_ff (q, clk, reset);
..
..
<functionality T_ff>
..
..
endmodule

Using Verilog
Levels of Abstraction
Verilog is both a behavioral and a
structural language.
Internals of each module can be
defined at four levels of abstraction,
depending on the needs of the
design.
The module behaves identically with
the
external
environment
irrespective
of
the
level
of
abstraction at which the module is
described.
Using Verilog
Continued.
Behavioral Level:
Highest level of abstraction
Module can be implemented in terms of
the desired design algorithm without
concern
for
the
hardware
implementation details.
Very similar to C programming
Dataflow Level:
Module designed by specifying dataflow.
The designer is aware of how data flows
between hardware registers and how
Vimal Kant Pandey
Digital
System
Design
the data isBy:processed
in
the
design
9
Using Verilog
Continued.
Gate Level:
Module implemented in terms of logic
gates like (and ,or) and interconnection
between gates
Similar to the design in terms of gate
level logic diagram.
Switch Level:
Module implemented with switches and
interconnects.
Lowest level of Abstraction
Using Verilog
10
Instance
A module provides a template from
which you can create actual objects.
When a module is invoked, Verilog
creates a unique object from the
template.
The process of creating a object from
module
template
is
called
instantiation.
The object is called instance.
Using Verilog
11
Example
module ripple_carry_counter(q, clk,
reset);
output [3:01 ]q;
input clk, reset;
//Four instances of the module T-FF are
created.
T_FF tff0(q[0], clk, reset);
T-FF tffl(q[1] ,q[0], reset);
T-FF tff2 (q[2] ,q[1] , reset) ;
T-FF tff3(q[3] ,q[2], reset) ;
endmodule
/ / Define the module T_FF.
module T_FF(q, clk, reset) ;
output q;
input clk, reset;
wire d;
D_FF dff0 (q, d, clk, reset) ;
not n1(d, q);
Note: In Verilog nesting of modules is illegal
endmodule
Using Verilog
12
Components of Simulation
Two styles of stimulus application is
possible.

Using Verilog
13
Basic Concepts
Lexical Conventions
White Space: It comprises
Blank spaces (\b)
tabs (\t)
newlines (\n)
Operators: It is of three types

Unary (e.g. a= ~b;)
Binary (e.g. z= a && b;)
Ternary (e.g. a = b ? c : d;)

Using Verilog
14
Continued..
Number Specification
Sized Number: Number is specified as
<size>'<base format> <number>

Legal base formats are:
Decimal (d or D)
Hexadecimal (h or H)
Binary (b or B)
Octal (o or O)

Using Verilog
15
Continued..
Unsized numbers
Numbers that are specified without a
<base format> specification are decimal
numbers by default.
Numbers that are written without a
<size> specification have a default
number of bits that is simulator- and
machine-specific (must be at least 32).

Using Verilog
16
Continued..
X or Z Values
Negative Numbers
specified by putting a minus sign before
the size for aconstant number.
Size constants are always positive

Using Verilog
17
Continued..
Underscore characters and question
marks
"-" is allowed anywhere in a number except the
first character.
is the Verilog HDL alternative for z in the
context of numbers.
Strings
sequence of characters that are enclosed by
double quotes
Using Verilog
18
Continued..
Identifiers and Keywords
Identifiers are names given to objects so that they can be
referenced in the design.
Identifiers are made up of alphanumeric characters, the
underscore ( _ ) and the dollar sign ( $ ) and are case
sensitive.
Identifiers start with an alphabetic character or an
underscore.
Cannot start with a number or a $ sign
Keywords are special identifiers reserved to define the
language constructs
Keywords are in lowercase

Using Verilog
19
Data Types
Value Sets

Using Verilog
20
Continued
Nets
Nets represent connections between hardware
elements.
Declared with keyword wire
Nets are one-bit values by default unless they
are declared explicitly as vectors
The default value of a net is z (except the
trireg net, which defaults to x).
Nets get the output value of their drivers. If a
net has no driver, it gets the value z

Using Verilog
21
Continued.
Registers
Declared by keyword reg and default
value is x
Registers
represent
data
storage
elements. Registers retain value until
another value is placed onto them.
In Verilog, the term register merely
means a variable that can hold a value.
Unlike a net, a register does not need a
driver.
Using Verilog
22
Continued.
Vectors
Nets or reg data types can be declared as vectors
If bit width is not specified, the default is scalar
(1-bit).
Vectors can be declared as [high# : low#] or
[low# : high#] but the left number in the squared
brackets is always the most significant bit of the
vector

Using Verilog
23
Continued.
It is possible to address bits or parts
of vectors.

Using Verilog
24
Integer, Real, and Time Register Data Types
Integer
declared by the keyword integer
default width for an integer is the hostmachine word size, which is implementation
specific but is at least 32 bits.
Registers declared as data type reg store
values as unsigned quantities, whereas
integers store values as signed quantities.

Using Verilog
25
Continued
Real
Declared by keyword real
Time
Keyword time
width for time register data types is implementation
specific but is at least 64 bits
system function $time is invoked to get the current
simulation time

Using Verilog
26
Continued
Arrays
Allowed for reg, integer, time, and vector register
data
Not allowed for real variables
accessed by <array-name> [<subscript>]
Multidimensional arrays are not permitted

Using Verilog
27
Continued.
Parameters
constants to be defined in a module by the keyword
parameter
cannot be used as variables
Parameter values for each module instance can be
overridden individually at compile time
Parameters can be changed at module instantiation or
by using the defparam statement

Using Verilog
28
System Tasks and Compiler Directives

System Tasks
Displaying information
Monitoring information

Using Verilog
29
Continued.
Monitoring information
$monitoron
$monitoroff
$start & $finish

Using Verilog
30
Continued.
Compiler Directives
Defined by using the ' <keyword> construct
`define & `include

Using Verilog
31
Modules and Ports

Module

Using Verilog
32
Continued.
Ports
Ports provide interface for by which a module can
communicate with its environment

Using Verilog
33
Port connection rules

Using Verilog
34
Connecting Ports to External Signals

There are two methods of making connections
between signals specified in the module
instantiation and the ports in a module definition:
Connecting by ordered list
Connecting ports by name
module Top;
module fulladd4 (sum, c-out, a, b, c-in) ;
Declare connection variables
output [3 : 01 sum;
eg [3:O]A,B;
output c-cout;
eg C-IN;
input [ 3 : 0 ] a, b;
wire [3:0] SUM;
input c-in;
wire C-OUT;
...
Instantiate fulladdl, call it fa-ordered. <module internals>
Signals are connected to ports in order (by
... position)
ulladd4 fa-ordered(SUM, C-OUT, A, B, C-IN);
endmodule
.
<stimulus>
ndmodule
Using Verilog
35
Continued.
Connecting ports by name

Using Verilog
36
Gate Level Modeling

Verilog supports basic logic gates as predefined
primitives.
These primitives are instantiated like modules
except that they are predefined in Verilog and do
notAvailable
need a module definition.
Gates
and
Nand
Or
Nor
Xor
Xnor
Buf/not
Bufif/notif
Using Verilog
37
Design of 4:1 Multiplexer: Verilog Code

// Module 4-to-1 multiplexer. Port list is taken exactly from the I/0 diagram.
module multiplx (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the 1/0 diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;
// Gate instantiations
// Create sln and son signals.
not (s0n, s0);
not (s1n, s1);
// 3-input and gates instantiated
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
// 4-input or gate instantiated
or (out, y0, y1, y2, y3 ) ;
endmodule

Using Verilog
38
Design of 4-bit full adder

1-bit Adder
4-bit Adder

Using Verilog
39
Verilog Code
1-bit adder

Using Verilog
40
Continued.
4-bit adder

Using Verilog
41
Gate Delays
Rise Delay: Delay associated with a o/p transition
to 1 from any value.
Fall Delay: Delay associated with o/p transition to

0 from any value.
Turn off Delay: Delay associate with o/p transition
to Z from another value.

Using Verilog
42
Min/Typ/Max Values
Min value
The min value is the minimum delay value that the
designer expects the gate to have.
Typ value
The typ value is the typical delay value that the designer
expects the gate to have.
Max value
The max value is the maximum delay value that the
designer expects the gate to have.

Using Verilog
43
Example

Using Verilog
44
Dataflow Modeling
In complex designs the number of gates is
very large
With gate densities on chips increasing
rapidly, dataflow modeling has assumed
great importance.
Currently, automated tools are used to
create a gate-level circuit from a dataflow
design description. This process is called
logic synthesis

Using Verilog
45
Continuous Assignment

Using Verilog
46
Continued.
Rules:
The left hand side of an assignment must always
be a scalar or vector net
It cannot be a scalar or vector register.
Continuous assignments are always active.

The assignment expression is evaluated as soon as one
of the right-hand-side operands changes and the value is
assigned to the left-hand-side net.
The operands on the right-hand side can be

registers or nets or function calls. Registers or
nets can be scalars or vectors.
Delay values can be specified for assignments in
terms of time units
Using Verilog
47
Continued.
Implicit Continuous Assignment
Delays
Regular Assignment Delay
Implicit Continuous Assignment Delay
Net Declaration Delay

Using Verilog
48
Continued.
Example
Regular Assignment Delay

Using Verilog
49
Continued.
Implicit Continuous Assignment Delay
Net Declaration Delay

Using Verilog
50
Operator Types

Using Verilog
51
Continued

Using Verilog
52
Arithmetic Operators
There are two types of arithmetic operators:
Binary and Unary
Continued.
Unary Operator
The operators + and - can also work as unary operators.
used to specify the positive or negative sign of the
operand.
Unary + or - operators have higher precedence than the
binary + or operator
Example
-4 //Negative 4
+5 //Positive 5

Using Verilog
54
Logical Operators
Logical operators follows the following conditions:
Logical operators always evaluate to a 1-bit value, 0
(false), 1 (true), or X (ambiguous).
If an operand is not equal to zero, it is equivalent to a
logical 1 (true condition).
If it is equal to zero, it is equivalent to a logical 0 (false
condition).
If any operand bit is X or z, it is equivalent to X
(ambiguous condition) and is normally treated by
simulators as a false condition.
Logical operators take variables or expressions as
operands.
Continued.
Examples

Using Verilog
56
Relational Operators
Relational operators:
greater-than (>),
less-than (<)
greater-than-or-equal-to (>=)
less-than-or-equal-to (<=)
If relational operators are used in an expression,

the expression returns
a logical value of 1 if the expression is true
0 if the expression is false.
If there are any unknown or z bits in the

operands, the expression takes a value X

Using Verilog
57
Equality Operators

Using Verilog
58
Bitwise Operators
It performs bit-by-bit operations on two operands.
If one operand is shorter than the other, it will be
bit extended with zero to match the length.
Example:
Reduction operator
Perform a bitwise operation on single bit-vector
operand and yield a 1-bit result.
Example:
Shift Operator
Logical Shift: vacant bit positions are filled with
zeros
Arithmetic Shift: use the context of the expression
to determine the value with which to fill the
vacated bits.
Example:
Concatenation Operator({,})
It provides a mechanism to append multiple
operands.
The operands must be sized.
Unsized operands are not allowed because the
size of each operand must be known for the
computation of result.
Replication Operator
Repetitive concatenation of the same number can
be expressed by using a replication constant.
Replication constant specifies how many times to
replicate the number inside the brackets ({}).
Conditional Operator
Example : 4:1 Multiplexer
4-bit Full Adder

Using Verilog
66
Behavioral Modeling
Structured Procedures: there are two structured
procedure statements: always and initial
All other behavioral statements can appear only
inside these structured statements.
Each always and initial statement represents a ,
separate activity flow in Verilog.
Each activity flow starts at simulation time 0.
The statements always and initial cannot be
nested
initial Statement
All statements inside this constitute initial block.
An initial block starts at time 0ns,executes only
once during simulation and then does not
executes again.
If there are multiple initial blocks, each block
starts to execute concurrently at 0ns.
Each block finishes execution independently of
other blocks.
Multiple behavioral statements must be grouped,
typically using the keywords begin and end.
Example
always Statement
All behavioral statements inside an always
statement constitute an always block.
The always statement starts at time 0 and
executes the statements in the always block
continuously in a looping fashion

Using Verilog
70
Procedural Assignments
Update values of reg, integer, real, or time
variables.
Syntax: <assignment> ::=<lvalue> =
<expression>
The left-hand side of a procedural assignment
<lvalue> can be one of the following:
A reg, integer, real, or time register variable or a
memory element
A bit select of these variables (e.g., addr[Ol)
A part select of these variables (e.g., addr[31:161)
A concatenation of any of the above
There are two types of procedural assignment

statements:
Blocking
Nonblocking

Using Verilog
71
Blocking assignments
Executed in the order they are specified in a
sequential block.
A blocking assignment will not block execution of
statements that follow in a parallel block.

Using Verilog
72
Nonblocking Assignments
Allows scheduling of assignments without
blocking execution of the statements that follow
in a sequential block.
A <= operator is used to specify nonblocking
assignments.

Using Verilog
73

Digital System Design Using Verilog HDL

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Digital System

Reference: Verilog HDL by Samir Palnitkar

By: Vimal Kant Pandey

There are two basic approaches to

By: Vimal Kant Pandey

Top Down Methodology

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Verilog is case sensitive

Module- Basic Building Block

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Operators: It is of three types

By: Vimal Kant Pandey

<size>'<base format> <number>

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Integer, Real, and Time Register Data Types

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

System Tasks and Compiler Directives

By: Vimal Kant Pandey

$start & $finish

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Modules and Ports

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Port connection rules

By: Vimal Kant Pandey

Connecting Ports to External Signals

By: Vimal Kant Pandey

Gate Level Modeling

Design of 4:1 Multiplexer: Verilog Code

By: Vimal Kant Pandey

Design of 4-bit full adder

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Fall Delay: Delay associated with o/p transition to

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey

It cannot be a scalar or vector register.

Continuous assignments are always active.

The operands on the right-hand side can be

By: Vimal Kant Pandey

By: Vimal Kant Pandey

Net Declaration Delay

By: Vimal Kant Pandey

By: Vimal Kant Pandey

By: Vimal Kant Pandey