VHDL Slides

VHDL Programming for
FPGAs
For syllabus please look into Appendix A in
another document.
Text book : Circuit Design with VHDL Volnei A.
Prdroni.
8/23/16, M. Madana Gopal, EW
System Engineer, UTS Pvt Ltd,
Malakpet, Hyderabad-500036
VHDL Course for MCEME,

Trimulgherry, Secundrabad,
Telangana - 500015
Xilinx FPGA Families
Old families
XC3000, XC4000, XC5200
Old 0.5m, 0.35m and 0.25m technology. Not recommended for modern
designs.
High-performance families
Virtex (220 nm)
Virtex-E, Virtex-EM (180 nm)
Virtex-II (130 nm)
Virtex-II PRO (130 nm)
Virtex-4 (90 nm)
Virtex-5 (65 nm)
Virtex-6 (40 nm) coming in 2009
Low Cost Family
Spartan/XL derived from XC4000
Spartan-II derived from Virtex
Spartan-IIE derived from Virtex-E
Spartan-3 (90 nm)
Spartan-3E (90 nm) logic optimized
Spartan-3A (90 nm) I/O optimized
Spartan-3AN (90 nm) non-volatile,
Spartan-3A DSP (90 nm) DSP optimized
Spartan-6 (45 nm) coming in 2009
8/23/16

Telangana - 500015
https://www.xilinx.com/products/silico
n-devices/soc.html
8/23/16

Telangana - 500015
8/23/16
http://www.xilinx.com/support/docum
entation/data_sheets/ds180_7Series_
Trimulgherry,
Secundrabad,
4
Overview.pdf
Telangana - 500015
8/23/16

Telangana - 500015
Part Marking
Ordering Information
An example of an ordering code for a
Xilinx FPGA is XC4VLX6010FFG668CS2. The
ordering code stands for:
XC4VLX Family (Virtex-4 LX)
60 Number of system gates or logic
cells (60,000 logic cells)
-10 Speed grade (-10 speed)
FFG Package type (Pb-free flip-chip
BGA)
668 number of pins (668 pins)
C Temperature grade (Commercial)
S2 Step 2
8/23/16

Telangana - 500015
https://www.xilinx.com/products/technology.html
8/23/16

Telangana - 500015
8/23/16
http://www.xilinx.com/support/docum
VHDL Course
for MCEME,
Trimulgherry,
Secundrabad,
8
entation/user_guides/ug112.pdf
Telangana - 500015
8/23/16
Virtex-EM(2)
Virtex-II(2)
Virtex-II Pro(2)
Virtex-II Pro X(2)
Virtex-II QPro/R(2)
17S00(1)
17V00(1)
18V00(1)
1700/E/D/L(1)
1800(1)
4000/E/XL/XV(1)
9500(1)
https://www.xilinx.com/support/answer9500XL(1)
navigation/information-and-specification/information9500XL IQ(1)
and-specification.html
9500XL XA(1)
9500XV(1)
CoolRunner XPLA3(1)
CoolRunner-II(1)
CoolRunner-II XA(1)
FPGA Device Families(1)
Other Products(1)
Platform Flash(1)
Platform Flash XA(1)
RocketPHY(1)
Trimulgherry,
Secundrabad,
9
Spartan-6Q(1)
Telangana - 500015
8/23/16

Telangana - 500015
10
Combinational Vs
Sequential Logic
8/23/16

Telangana - 500015
11
Combinational Vs
Sequential Logic
8/23/16

Telangana - 500015
12
C - Language
Here the C compiler executes the
statements sequentially. Compilation,
Debug(if errors correct recompile) &
Execute if no errors.
In VHDL both sequential & concurrent
language constructs are available.
Sequential language constructs are to
used only inside Process a concurrent
construct.
8/23/16

Telangana - 500015
13
C - Language
All the C language constructs
which are available in VHDL are
to be only used inside the
PROCESS a concurrent
construct.
Can you name some examples
of C language constructs.
8/23/16

Telangana - 500015
14
C - Language
Sections of C language :
1.Declaration part
2.Read the input values
3.Perform operations or algorithms
on the input values to get required
outputs
4.Write/display the output values
to the monitor
8/23/16

Telangana - 500015
15
C Language
header files, Macros, declaration of Variables etc.,
8/23/16

Telangana - 500015
16
VHDL Design Flow
8/23/16

Telangana - 500015
17
VHDL Reserve Words
8/23/16

Telangana - 500015
18
VHDL - Sections
8/23/16

Telangana - 500015
19
VHDL Sections (Inside

Library)
8/23/16

Telangana - 500015
20
Library declaration inside VHDL

Code
8/23/16

Telangana - 500015
21
IEEE Library
8/23/16

Telangana - 500015
22
Entity
8/23/16

Telangana - 500015
23
Architecture
8/23/16

Telangana - 500015
24
DECODER2x4 - Entity
8/23/16

Telangana - 500015
25
DECODER2x4 - Structural MODEL
8/23/16

Telangana - 500015
26
DECODER2x4 - Dataflow
MODEL
8/23/16

Telangana - 500015
27
DECODER2x4 - Behavioral
MODEL
8/23/16

Telangana - 500015
28
8/23/16

Telangana - 500015
29
8/23/16

Telangana - 500015
30
8/23/16

Telangana - 500015
31
Structural MODEL
8/23/16

Telangana - 500015
32
8/23/16

Telangana - 500015
33
Structural modeling
8/23/16

Telangana - 500015
34
8/23/16

Telangana - 500015
35
8/23/16

Telangana - 500015
36
Dataflow & Behavioral

Modeling
8/23/16

Telangana - 500015
37
Dataflow & Behavioral

Modeling
8/23/16

Telangana - 500015
38
Dataflow modeling
8/23/16

Telangana - 500015
39
Dataflow modeling
8/23/16

Telangana - 500015
40
8/23/16

Telangana - 500015
41
Dataflow modeling
8/23/16

Telangana - 500015
42
Dataflow modeling
8/23/16

Telangana - 500015
43
8/23/16

Telangana - 500015
44
Dataflow modeling
8/23/16

Telangana - 500015
45
8/23/16

Telangana - 500015
46
8/23/16

Telangana - 500015
47
8/23/16

Telangana - 500015
48
8/23/16

Telangana - 500015
49
8/23/16

Telangana - 500015
50
ALU
8/23/16

Telangana - 500015
51
8/23/16

Telangana - 500015
52
8/23/16

Telangana - 500015
53
8/23/16

Telangana - 500015
54
8/23/16

Telangana - 500015
55
8/23/16

Telangana - 500015
56
8/23/16

Telangana - 500015
57
8/23/16

Telangana - 500015
58
8/23/16

Telangana - 500015
59
8/23/16

Telangana - 500015
60
8/23/16

Telangana - 500015
61
8/23/16

Telangana - 500015
62
8/23/16

Telangana - 500015
63
8/23/16

Telangana - 500015
64
8/23/16

Telangana - 500015
65
8/23/16

Telangana - 500015
66
8/23/16

Telangana - 500015
67
D-FF Behavioral Modeling
8/23/16

Telangana - 500015
68
8/23/16

Telangana - 500015
69
Counter Behavioral
Modeling
8/23/16

Telangana - 500015
70
8/23/16

Telangana - 500015
71
8/23/16

Telangana - 500015
72
8/23/16

Telangana - 500015
73
8/23/16

Telangana - 500015
74
DATA TYPES Predefined data types
8/23/16

Telangana - 500015
75
8/23/16

Telangana - 500015
76
8/23/16

Telangana - 500015
77
8/23/16

Telangana - 500015
78
8/23/16

Telangana - 500015
79
8/23/16

Telangana - 500015
80
8/23/16

Telangana - 500015
81
8/23/16

Telangana - 500015
82
Examples
8/23/16

Telangana - 500015
83
8/23/16

Telangana - 500015
84
DATA TYPES Userdefined data

types
8/23/16

Telangana - 500015
85
8/23/16

Telangana - 500015
86
What is encoding Sequentially

done by compiler
8/23/16

Telangana - 500015
87
DATA TYPES Userdefined data

types, SUBTYPE
8/23/16

Telangana - 500015
88
DATA TYPES Pre/Userdefined data

types
8/23/16

Telangana - 500015
89

types
8/23/16

Telangana - 500015
90

types
8/23/16

Telangana - 500015
91
DATA TYPES Signed/Unsigned data

types
8/23/16

Telangana - 500015
92
8/23/16

Telangana - 500015
93
8/23/16

Telangana - 500015
94
8/23/16

Telangana - 500015
95
DATA CONVERSION
8/23/16

Telangana - 500015
96
8/23/16

Telangana - 500015
97
8/23/16

Telangana - 500015
98
8/23/16

Telangana - 500015
99
8/23/16

Telangana - 500015
100
8/23/16

Telangana - 500015
101
CLOCK used in Test Benches
8/23/16

Telangana - 500015
102
OPERATORS
8/23/16

Telangana - 500015
103
8/23/16

Telangana - 500015
104
Still incomplete Yet to

update
8/23/16

Telangana - 500015
105

VHDL Slides

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VHDL Slides

Uploaded by

Copyright:

Available Formats

VHDL Programming for

VHDL Course for MCEME,

Xilinx FPGA Families

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Design Flow

VHDL Course for MCEME,

VHDL Reserve Words

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Sections (Inside

VHDL Course for MCEME,

Library declaration inside VHDL

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

DECODER2x4 - Structural MODEL

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

Dataflow & Behavioral

VHDL Course for MCEME,

Dataflow & Behavioral

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,

VHDL Course for MCEME,