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Module #5 Inverters
Agenda
1. Inverters
- Static Characteristics
- Switching Characteristics
Announcements
1. Read Chapters 5, & 7
Module #5
Page 1
Inverters
Inverters
- an inverter is a basic gate that complements the input
- we study the invert in order to understand the Static and Dynamic performance
- once we do this, we can model more complex logic gates as "equivalent inverters" and use the
same analysis.
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Inverters
Inverters
- The "Voltage Transfer Characteristics" (VTC) of an ideal inverter
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Inverters
Inverters
- Graphically, this looks like:
VDD = HIGH
Vin
Vout
GND = LOW
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Inverters
Logic Levels
- We need to define boundaries when the signal is considered HIGH or LOW
- these are called the "Logic Levels"
VDD = HIGH
GND = LOW
HIGH
LOW
Vin
Vout
t
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Static Behavior
- "Static" or "DC" refers to the gate's operation when the inputs are NOT changing
- also called "Steady State"
- if we plotted Vout vs. Vin of an Inverter, we would get
Vout
Logic HIGH
Logic LOW
Vin
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Static Behavior
- the region in the middle is not definitely a HIGH or a LOW because of:
- Power Supply Variation
- Process
- Noise
Vout
Vin
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DC Specifications
- we need to be able to guarantee operation of the gate over all possible conditions
- the limits on guaranteed operation are called "specifications"
- Specifications can give limits on the worst case situations
- Specifications can also give limits on typical situations
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DC Specifications
- in a real inverter VTC, the output doesn't switch
instantaneously
- there are two critical points on the real VTC curve
which occur when the slope of Vout(Vin)= -1
- VIL is the input low voltage which corresponds to an
output high voltage with a slope of -1.
- VIH is the input high voltage which corresponds to
an output low voltage with a slope of -1
- other critical points are:
- VOH is the output voltage when the
output level is logic "1"
- VOL is the output voltage when the
output level is logic "0"
- Vth is the point at which Vout=Vin
EELE 414 Introduction to VLSI Design
Module #5
Page 9
DC Input Specifications
VIH
VIL
VDD
HIGH
VIH
Vin
VIL
LOW
VSS
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DC Output Specifications
VOH
VOL
HIGH
VDD
VOH
Vout
LOW
VOL
VSS
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= (VOHmin - VIHmin)
= (VILmax - VOLmax)
Vout
VDD
VOH
VOL
VSS
Vin
HIGH
Noise Margin
Noise Margin
LOW
VDD
HIGH
VIH
VIL
LOW
VSS
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DC Power Specifications
- the total DC power dissipated by an IC is given by:
PDC VDD I DC
- for a given gate, the current drawn will vary depending on the logic level
Driving a Logic HIGH:
I DC 1 Vin low
I DC 2 Vin high
- the gate will be in each one of these states 50% of the time
- if we assume the output voltage will swing from 0 to V DD, we can estimate the average output
voltage as VDD/2
- a rough estimate of the DC power is:
PDC
VDD
I DC Vin low I DC Vin high
2
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Area
- as designers, we can adjust the sizes of L and W.
- we know that there is additional area required to fabricate the MOSFET
- active regions (surrounding FOX)
- channel Length (Y)
- substrate contacts
- but, as a practical measure, we talk about the area of a circuit as WL
- while we know this isn't the full area that the device takes, it gives us a standard way to compare
the sizes of different layouts.
- it is widely accepted that the area of a device is WL
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Inverter Design
Inverter Implementations
- now we turn our attention to the circuit level implementation of the inverter
- there are many ways to create an inverter using MOSFETs
1) inverter with resistive-load
2) inverter with enhancement n-Type MOSFET load operating in the linear region
3) inverter with enhancement n-Type MOSFET load operating in the saturation region
4) inverter with depletion n-Type MOSFET load
5) CMOS inverter
- the most common type of inverter in VLSI is CMOS. This is due to the low static power
consumption
- however, it is worth while to briefly look at other types of inverter implementations in case you use
a fab that doesn't have PMOS
- for example, the Montana Microfabrication Facility (MMF)
- no N-Well & PMOS
- BUT, we can still design inverters using different circuit styles.
EELE 414 Introduction to VLSI Design
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Resistive-Load Inverter
Resistive-Load Inverter
- this circuit consists of an enhancement-type, N-Channel MOSFET as the driver
- a load resistor is connected between V DD and the Drain (Vout) of the MOSFET
- the gates that this inverter drives are assumed to be of the same configuration so there
is no DC load current looking into their gate terminals.
- Vout = VDS
- Vin = Vgs
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Resistive-Load Inverter
Resistive-Load Inverter
- we need a relatively high resistor (k) so we can implement the resistor using
either a diffused or undoped-poly resistor
- this resistor takes a large amount of die area to implement
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Resistive-Load Inverter
Resistive-Load Inverter
- we solve for Vout(Vin) using KVL where:
Vout VDD RL I R
I R I DS
VDD Vout
RL
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Resistive-Load Inverter
Resistive-Load Inverter
- we solve for VIH and VIL
- applying Vin=VGS=logic "0" or "1"
- determining the mode of operation (cut-off, linear, sat)
- creating an equation relating I DS, Vout, and Vin
- remember that VIH and VIL are defined as the input voltage
when the output has a slope of -1
- then we need to:
- differentiate the equation with respect to V in
- plug in (dVout/dVin)=-1
- solve for VIH or VIL
- note that the solution will be quadratic (i.e., have two
solutions). We pick the logical solution
i.e., the smaller solution for VIL
and
the larger solution for VIH
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Resistive-Load Inverter
Resistive-Load Inverter
- these solutions yield:
VOH VDD
2
VOL
1
1
2 VDD
VDD VT 0
VDD VT 0
k n RL
k n RL
k n RL
VIH VTO
VIL VT 0
8 VDD
1
3 k n RL k n RL
1
k n RL
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Resistive-Load Inverter
Resistive-Load Inverter
- notice that these solutions only depend on k nRL
- we have control over W & L, which alters k n
- we have control over RL by altering the
shape of the resistor
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Active-Load Inverter
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Active-Load Inverter
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CMOS Inverter
CMOS Inverter
- the CMOS inverter uses an NMOS and a PMOS transistor in a complementary push/pull
configuration
- for a Logic "1" output, the PMOS=ON and the NMOS=OFF
- for a Logic "0" output, the PMOS=OFF and the NMOS=ON
- this configuration has two major advantages:
1) low static power consumption : due to one MOSFET always being off
2) a sharp and symmetric VTC profile giving full swing signals (1=V DD, 0=VSS)
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CMOS Inverter
CMOS Inverter
- basic operation, complementary switches
Input = 0
Input = 1
VDD
S
VDD
PMOS = ON
PMOS = OFF
G
D
ILOAD
ILOAD
1
D
G
S
NMOS = OFF
GND
NMOS = ON
GND
EELE 414 Introduction to VLSI Design
Module #5
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CMOS Inverter
VGS ,n Vin
VDS ,n Vout
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CMOS Inverter
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CMOS Inverter
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CMOS Inverter
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CMOS Inverter
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CMOS Inverter
Region E
- Now let's move Vin above (VDD+VT,p)
(Vin = 5v, Vout = 0v)
- the NMOS transistor is ON since
VGS,n > VT,n i.e., 5 > 1
- the NMOS transistor is in linear since
VDS,n < (VGS,n-VT,n) i.e., ~0 < (5 - 1)
- the PMOS transistor is OFF since
VGS,p > VT,p i.e., (5-5) > -1 (cut-off)
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CMOS Inverter
Summary
Region
A
B
C
D
E
NMOS
PMOS
cut-off
linear
saturation linear
saturation saturation
linear saturation
linear cut-off
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CMOS Inverter
VOH VDD
VOL VSS
- Note that VDD is typically the power supply and V SS is typically GND.
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CMOS Inverter
- VIL is defined as the input voltage that corresponds to the higher of the two output voltages with a
slope of -1.
- we know the modes of operation for the transistors in this region:
NMOS = saturation
PMOS = linear
- we also know from KCL that I D,p = ID,n
- from this, we can write our first current equation:
I D ,n ( sat ) I D , p ( lin )
kp
kn
2
2
VGS ,n VT 0,n 2 VGS , p VT 0, p VDS , p VDS
,p
2
2
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CMOS Inverter
- remembering the relationships between V in & Vout, and VGS & VDS:
VGS ,n Vin
VDS ,n Vout
- we can write:
kp
kn
2
2
Vin VT 0,n 2 Vin VDD VT 0, p Vout VDD Vout VDD
2
2
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CMOS Inverter
d kn
d kp
2
2
in
T 0,n
dVin 2
dVin 2
- the left-hand-side is straight forward to perform a partial derivative on (with respect to Vin),
but the right-hand side consists of two products that must be differentiated using the product rule.
Remember the product rule:
Z f ( x, y ) g ( x , y )
dZ df
dg
g ( x, y )
f ( x, y )
dx dx
dx
EELE 414 Introduction to VLSI Design
Module #5
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CMOS Inverter
d kn
d kp
2
in
T 0, n
dVin 2
dVin 2
Product #1
Product #2
- the left-hand-side is straight forward to perform a partial derivative on (with respect to Vin),
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CMOS Inverter
RHS
d
dVin
kp
df
dg
g ( x, y )
f ( x, y )
dx
dx
df
dg
g ( x, y )
f ( x, y )
dx
dx
kp
dVout dVout
dVout
2 1 Vout VDD Vin VDD VT 0, p
Vout VDD Vout VDD
2
dVin
dVin
dVin
kp
dVout
dVout
Combine two like expressions
RHS 2 1 Vout VDD Vin VDD VT 0, p
2 Vout VDD
2
dVin
dVin
RHS
dVout
dVout
RHS k p Vout VDD Vin VDD VT 0, p
Vout VDD
dVin
dVin
dVout
dVout
RHS k p Vin VDD VT 0, p
Vout VDD Vout VDD
dVin
dVin
Pull out 2
Rearrange expression
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CMOS Inverter
dVout
dVout
k n Vin VT 0, n k p Vin VDD VT 0, p
Vout VDD Vout VDD
dVin
dVin
- let's plug in the condition we're solving for (dV out/dVin = -1)
V V V
2 V V V
in
DD
out
T 0, p
in
T 0, p
VDD
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CMOS Inverter
kn k p
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CMOS Inverter
kp
kp
kp
kn
2 Vout VT 0, p VT 0,n VDD
kp
kp
kp
kp
VIL
kn k p
kp kp
kR
kn
kp
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CMOS Inverter
VIL
NOTE:
- this still depends on Vout. This means to get a numerical solution, we must solve this together with
our expression relating the drain currents:
kp
kn
2
2
VIL VT 0,n 2 VIL VDD VT 0, p Vout VDD Vout VDD
2
2
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CMOS Inverter
- VIH is defined as the input voltage that corresponds to the lower of the two output voltages with a
slope of -1.
- we know the modes of operation for the transistors in this region:
NMOS = linear
PMOS = saturation
- we also know from KCL that I D,p = ID,n
- from this, we can write our first current equation:
I D ,n ( lin ) I D , p ( sat )
kp
kn
2
2
2 VGS ,n VT 0,n VDS ,n VDS ,n VGS , p VT 0, p
2
2
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CMOS Inverter
- remembering the relationships between V in & Vout, and VGS & VDS:
VGS ,n Vin
VDS ,n Vout
- we can write:
kp
kn
2
2
2 Vin VT 0,n Vout Vout
Vin VDD VT 0, p
2
2
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CMOS Inverter
- we are looking for when the derivative of dV out/dVin = -1 so we differentiate both sides:
d kn
d kp
2
2
dVin 2
dVin 2
- once again, we have a situation where we are differentiating an expression that contains product
terms
we use the product rule again:
Z f ( x, y ) g ( x , y )
dZ df
dg
g ( x, y )
f ( x, y )
dx dx
dx
EELE 414 Introduction to VLSI Design
Module #5
Page 45
CMOS Inverter
d
dVin
d kp
kn
in
T 0,n
out
out
out
in
DD
T 0, p
2
dVin 2
Product #1
Product #2
- the right-hand-side is straight forward to perform a partial derivative on (with respect to Vin),
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CMOS Inverter
LHS
d kn
dVin 2
df
dg
g ( x, y )
f ( x, y )
dx
dx
df
dg
g ( x, y )
f ( x, y )
dx
dx
dVout dVout
dVout
k n
Vout Vout
2 1 Vout Vin VT 0,n
2
dVin dVin
dVin
dVout
dVout
k
2 Vout
LHS n 2 1 Vout Vin VT 0,n
2
dV
dV
in
in
dVout
dVout
Vout
LHS k n 1 Vout Vin VT 0,n
dV
dV
in
in
LHS
dVout
LHS k n Vin VT 0,n
dVin
dVout
dVin
Vout Vout
Combine two like expressions
Pull out 2
Rearrange expression
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CMOS Inverter
dVout
k n Vin VT 0,n
dVin
dVout
dVin
Vout Vout
k p Vin VDD VT 0, p
- let's plug in the condition we're solving for (dV out/dVin = -1)
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CMOS Inverter
kn k p
EELE 414 Introduction to VLSI Design
Module #5
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CMOS Inverter
kp
VIH
kp
VDD
kp
kp
kn
k
VT 0,n 2 n Vout
kp
kp
kn k p
kp kp
VT 0, p
kR
kn
kp
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CMOS Inverter
VIH
VIH
NOTE:
- this expression again depends on V out. This means to get a numerical solution, we must
solve this together with our expression relating the drain currents (where V in=VIH):
kp
kn
2
2
2 VIH VT 0,n Vout Vout VIH VDD VT 0, p
2
2
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CMOS Inverter
VOL 0
VOH VDD
VIL
VIH
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- since we know the modes of operation we can write KCL to get our current equation:
I D ,n ( sat ) I D , p ( sat )
kp
kn
2
2
VGS ,n VT 0,n VGS , p VT 0, p
2
2
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- remembering the relationships between V in & Vout, and VGS & VDS:
VGS ,n Vin
VDS ,n Vout
- we can write:
kn
Vin VT 0,n 2 k p Vin VDD VT 0, p 2
2
2
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kp
kn
2
2
Vin VT 0,n Vin VDD VT 0, p
2
2
- let's walk through the steps of this solution:
in VT 0 , n
kp
kn
Vin VDD VT 0, p
Divide by sqrt(kp)
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Vin VT 0,n
Vin VT 0,n
Vin VT 0,n
Vin
kp
kn
kp
kn
kp
kn
kp
kn
Vin VDD VT 0, p
Vin VDD VT 0, p
Vin
Vin VT 0,n
kp
kn
kp
kn
VDD VT 0, p
VDD VT 0, p
kp
k
VT 0,n p VDD VT 0, p
Vin 1
k n
kn
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kp
VT 0,n
Vin
kn
Vin
kp
k n
1
VDD VT 0, p
kR
VT 0,n
1
kR
Substitute in kr=sqrt(kn/kp)
1
VDD VT 0, p
kR
VT 0,n
Vth
VDD VT 0, p
1 1
k R
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1
VDD VT 0, p
kR
VT 0,n
Vth
1
kR
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1
VDD VT 0, p
kR
VT 0,n
1
kR
1
1
Vth 1
VDD VT 0, p
T
0
,
n
k
k
R
R
Vth Vth
1
1
VT 0,n
VDD VT 0, p
kR
kR
Vth VT 0,n
1
1
VDD VT 0, p Vth
kR
kR
Vth VT 0,n
1
VDD VT 0, p Vth
kR
Vth VT 0,n
1
k R VDD VT 0, p Vth
EELE 414 Introduction to VLSI Design
Module #5
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VDD VT 0, p Vth
k
k R n
kp
Vth VT 0,n
- an Ideal inverter puts the switching threshold directly in the middle of the voltage swing:
vth ,ideal
VDD
kn
k
p
ideal
0.5 VDD VT 0, p
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kn
k
p
0.5 VDD VT 0, p
ideal
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- remembering the expression for k n/kp, we can see that Cox will not have an effect:
W
k
L
kR n
kp
W
p Cox
L
n Cox
W
L
W
p
L
kn
k
p
L
1
W
p
ideal
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L
W
n
p
- this means that for the given electron mobility of a process, we can size the PMOS and NMOS
transistors in order to move the switching threshold to V DD/2
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- sizing of the transistor can have a large impact on the noise margins and sensitivity of the inverter
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I D (max)
kp
kn
2
2
VGS ,n VT 0,n VGS , p VT 0, p
2
2
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Wp
Wn
n
p
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Oxides of
Driver
Junctions
of Driver
Interconnect
Oxide of
Receiver
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iC C
dV
dt
VDD
VDD
PMOS = ON
PMOS = OFF
G
D
Ic
0
D
0
Ic
Cload
Cload
G
S
NMOS = OFF
GND
NMOS = ON
GND
EELE 414 Introduction to VLSI Design
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PHL t1 t0
PLH t3 t 2
1
1
V50% VOL VOH VOL VOH VOL
2
2
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NMOS in Saturation
NMOS in Linear
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iC iD ,n Cload
dt Cload
dVout
dt
dVout
iD , n
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t1' t0
t t1'
Vout VOH VT ,n
t t 0
Vout VOH
dt Cload
dVout
i
D ,n sat
t1 t
'
1
t t 0
dt Cload
t t1'
Vout V50%
dVout
i
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PHL
2 VT ,n
4VDD VT ,n
Cload
ln
1
k n VOH VT ,n VOH VT ,n
VOH VOL
PHL
2 VT ,n
4VDD VT ,n
Cload
ln
1
k n VDD VT ,n VDD VT ,n
VDD
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PLH
2 VT , p
4 VDD VT , p
Cload
ln
1
VDD
k p VDD VT , p VDD VT , p
- these solutions are accurate from the standpoint that we use the exact current in the
transistors in our derivation of delay.
- these are still estimates and dont include channel-length-modulation or small-geometry
effects
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PHL
Cload VHL
Cload VHL
1
I avg , HL
iD sat iD lin
2
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PHL
PLH
Cload VHL
1
iD sat Vin VOH , Vout VOH iD lin Vin VOH ,Vout V50%
2
Cload VLH
1
iD sat Vin VOL , Vout VOL iD lin Vin VOL , Vout V50%
2
- this technique tends to be faster and easier to use than the differential equation method.
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- we can use either the (1) differential equation or the (2) average current technique to solve for
these
- in these transitions, the transistors again operate in both the saturation and linear regions
- the only difference is that the limits of the transition are V 10% and V90%
EELE 414 Introduction to VLSI Design
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Non-ideal Inputs
- in all of these derivations, we have assumed a perfect step input.
- if the input is not a perfect step (i.e., it has a finite delay or rise time), it will
increase the delay of the gate
- we can use an RMS estimation to account for the non-ideal input:
PHL ( actual )
PLH ( actual )
- we can also estimate the delay of the input if we are only given its rise/fall time by using:
rise
2
fall
2
PLH
PHL
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Non-ideal Inputs
- we can apply this technique to the rise and fall times also:
2
2
2
rise
( actual )
rise ( to _ step _ input )
fall ( of _ input )
2
2fall ( actual ) 2fall ( to _ step _ input ) rise
( of _ input )
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PHL
PLH
Cload VHL
1
iD sat Vin VOH ,Vout VOH iD lin Vin VOH , Vout V50%
2
Cload VLH
1
iD sat Vin VOL , Vout VOL iD lin Vin VOL , Vout V50%
2
- in this expression, we can insert our timing spec in for PHL or PLH
- the RHS of the expression must evaluate to be less than or equal to the timing spec
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Interconnect
- one of the components in the load capacitance is the interconnect.
- the interconnect refers to the polysilicon and metal layers that are used to connect
the gates together.
- as sizes on-chip shrink, weve seen that the scaling of interconnect is a big problem because the
delay actually increases as you get smaller.
- in addition, the delay scales quadradically
with length meaning that intra-module traces
and global interconnect can create
significant timing challenges.
- in modern processes, the delay of the
interconnect is actually more than the
switching delay of the transistors.
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Interconnect Modeling
- modeling of the interconnect describes the equivalent circuits we use to describe the electrical
behavior of the materials.
- the type of model we use is a trade-off between accuracy and simulation time
- we typciall use 1 of the 3 following models:
Typical Uses
1) Lumped Capacitance
2) RC network
3) Transmission Line
inter-module
intra-module and global
global and off-chip
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Interconnect Modeling
- we choose the appropriate model based on the rise/fall time of the driver relative to the
prop delay of the interconnect
- the prop delay (tprop) is the time it takes for the wave to travel down the length of the interconnect:
- the velocity of a wave in a dielectric is given by:
c
r
t prop
length
v
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Interconnect Modeling
- we move between a lumped (C or RC) and a distributed (transmission line) model as follows:
Lumped
rise 2.5
Distributed
rise 2.5
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Interconnect Resistance
- resistance is based on the geometry and materials of the interconnect
l
RS # _ of _ squares
A
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Interconnect Capacitance
- capacitance depends on the surface area of the conductor, the insulating materials between
the conductors, and the distance between the conductors.
A
t
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Interconnect Capacitance
- interconnect modeling becomes a complex problem due to the 3D geometries present on-chip
- we typically take a guess at the capacitance of the interconnect for initial simulations.
- once we start physically laying out our design, we can use the CAD tool to extract the actual
capacitance and back annotate it into our simulation.
- we then run a new simulation with accurate capacitance models to
verify timing is still met post-layout.
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Interconnect Capacitance
- Cross-talk refers to the noise that is generated on a line due to capacitive coupling from
neighboring lines that are switching.
- as geometries get smaller, lines are closer together so capacitance goes up.
- we can reduce cross-talk by separating the traces or inserting ground lines between the
signals, but this takes area.
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Elmore Delay
- when we model interconnect using RC networks, it doesnt take many branches in the net
before the KVL/KCL solution for the delay gets complex.
- Elmore Delay is a technique to estimate the overall delay between two nodes of an RC network
tree.
- in Elmore Delay, we find the equivalent RC network of the path between two nodes by:
- summing the delay of each segment in our path-of-interest
- we construct a set of RC networks as seen by our path-of-interest and then sum them together
- we walk through the series resistance in our path-of-interest.
- for each resistor node in our path-of interest, we include RCs in our expression as follows:
- Cs NOT in our path-of-interest are included as (R segCx)
- Cs that ARE in our path-of-interest cant be seen if they are on the far side
of a resistor in our path-of-interest
- as we get to the end of our path-of-interest, we can see all of the downstream
Capacitances past our end-node.
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Elmore Delay
- example: Find the expression for the equivalent RC from V in to node 7:
D 7 R1 C1 R1 C2 R1 C3 R1 C4 R1 C5
R1 R6 C6
R1 R6 R7 C7 R1 R6 R7 C8
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iC Cload
dVout
dt
- since the current consumed is proportional to the number of times that the gate switches, we
need to make an assumption to the number of times per second that V out switches
- since we have a binary system, we can assume that the output will be a 0 50% of the time
and a 1 50% of the time.
- we can model the voltage on V out as a periodic square wave
EELE 414 Introduction to VLSI Design
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Pavg
1
v(t ) i (t )dt
T 0
T/2 T
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Pavg
Pavg
1
T
1
Pavg
T /2
Vout Cload
2
Vout
Cload
2
dVout
dt
T /2
dt
DD
out
Cload
T /2
2
Vout
Cload
2
dVout
dt
dt
T /2
1
2
Cload VDD
T
2
Pavg f Cload VDD
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Q
V
I AVG
Q C V
T
T
C V 1
2
2
Cload Vout
f Cload Vout
T
T
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Pavg
1
2
Cload VDD
time
2
Pavg Cload VDD
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Ring Oscillator
Ring Oscillator
- if we connect a chain of inverters in a loop
and have an ODD number of inverters,
the circuit is inherently unstable.
- the circuit will oscillate between a
0 and 1 indefinitely.
- the frequency of the oscillation depends
on the gate delay of the inverter.
- this type of circuit is commonly used
to test the device delay of a given
process.
- this can also be used to create a clock.
- the clock frequency of the ring oscillator
is not typically controlled tight enough to be
used as the system clock.
1
2 ninv inv
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Super Buffer
Super Buffer
- off-chip capacitances are typically an order of magnitude larger than on-chip capacitances.
- VLSI gates that are used in logic circuitry are sized to drive other gates of comparable size.
- if these smaller gates are connected to a much larger load capacitance, they are not sized
optimally.
- a gate can typically not drive a capacitance that has a much larger capacitance than its own
junction capacitance.
- a super buffer is a circuit that consists of a series of gates, each with a increasingly larger
size and drive strength.
- we define the relative size of each subsequence gate using the optimal sizing factor ( )
- we start with a typical logic gate and then design a subsequent stage that is larger by a factor of
- we continue to add stages until the final capacitance that is to be driven (C load) is a factor
of larger than the last state of the super buffer.
- we define the number of stages in the super buffer as N
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Super Buffer
Super Buffer
- we define Cg as the gate capacitance of the next state.
- we define Cd as the output drain capacitance of current stage.
- we can derive an expression to find the total delay as a function of (N, ).
- this expression gives us a relationship between N and .
- we can differentiate this expression to find the optimal scaling factor:
ln 1
Cd
Cg
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Super Buffer
Super Buffer
- we first find.
- this defines how much larger each subsequent stage is relative to its driving stage
- we continue to add stages until the final C g that can be driven is Cload
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