Introduction

to VLSI Design

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

EE414 VLSI Design

What is this course is

about?

Introduction to digital integrated circuits.

CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.

What will you learn?

Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability

EE414 VLSI Design

Digital Integrated Circuits

Introduction: Issues in digital design

The CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
Interconnect: R, L and C
Timing
Arithmetic building blocks
Memories and array structures

EE414 VLSI Design

Digital Integrated Circuits

What is meant by VLSI?
Brief history of evolution
Todays Chips
Moores Law
Machines Making Machines
VLSI Facts of Life

EE414 VLSI Design

What is a VLSI Circuit?

VERY LARGE SCALE

A circuit that has 10k

~ 10M transistors on a
single chip
Still growing as
number of transistors
on chip quadruple
every 24 months
(Moores law!)
EE414 VLSI Design

INTEGRATED CIRCUIT

Technique where many

circuit components
and the wiring that
connects them are
manufactured
simultaneously on a
compact chip (die)

Brief History
The First Computer: Babbage Difference Engine
(1832)
Executed basic
operations (add, sub,
mult, div) in arbitrary
sequences
Operated in two-cycle
sequence, Store, and
Mill (execute)
Included features like
pipelining to make it
faster.

EE414 VLSI Design

Complexity: 25,000
parts.

The Electrical Solution

More cost effective
Early systems used relays to make simple logic
devices
Still used today in some train safety systems
The Vacuum Tube
Originally used for analog processing
Later, complete digital computers realized
High Point of Tubes: The ENIAC
18,000 vacuum tubes
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80
ft long, 8.5 ft high, several feet wide

ENIAC - The first electronic computer

(1946)

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Dawn of the Transistor Age

1947: Bardeen and Brattain

create point-contact transistor
w/two PN junctions. Gain = 18
1951: Shockley develops
junction transistor which can
be manufactured in quantity.
EE414 VLSI Design

Early Integration

Jack Kilby, working at Texas Instruments,

invented a monolithic integrated circuit
in July 1959.
He had constructed the flip-flop shown in
the patent drawing above.
EE414 VLSI Design

Early Integration
In mid 1959, Noyce develops
the first true IC using planar
transistors, back-to-back pn
junctions for isolation, diodeisolated silicon resistors and
SiO2 insulation with evaporated
metal wiring on top

EE414 VLSI Design

Practice Makes Perfect

1961: TI and Fairchild introduce
first logic ICs (cost ~ $50 in
quantity!). This is a dual flip-flop
with 4 transistors.

1963: Densities and yields

improve. This circuit has
four flip-flops.
EE414 VLSI Design

Practice Makes Perfect

1967: Fairchild markets the first
semi-custom chip. Transistors
(organized in columns) can be
easily rewired to create
different circuits. Circuit has
~150 logic gates.
1968: Noyce and Moore leave Fairchild to
form Intel. They raise $3M in two days
and move to Santa Clara. By 1971 Intel
had 500 employees; by 1983, 21,500
employees
and $1.1B in sales.
EE414 VLSI Design

The Big Bang

1970: Intel starts selling a 1k
bit RAM, the 1103. Its density
and cost make it the only
game in town.

EE414 VLSI Design

1971: Ted Hoff at Intel designed

the first microprocessor. The
4004 had 4-bit busses and a
clock rate of 108 KHz. It had
2300 transistors and was built

Exponential Growth
1972: 8088 introduced. Had
3,500 transistors supporting a
byte-wide data path.

1974: Introduction of the

8080. Had 6,000 transistors
in a 6 um process. The clock
rate was 2 MHz.
EE414 VLSI Design

Today
Many disciplines have contributed to the current state
of the art in VLSI Design:
Solid State Physics
Materials Science
Lithography and fab
Device modeling
To come up with chips like:

EE414 VLSI Design

Circuit design and

layout
Architecture design
Algorithms
CAD tools

Intel Pentium
~3.5M
transistors

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Pentium Pro
Actually a MCM comprising
of microprocessor and L2
cache

Why not make it

on one chip?

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Sun UltraSparc

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Pentium 4

0.18-micron process technology

(2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz)
Introduction date: August 27, 2001
(2, 1.9 GHz); ...; November 20,
2000 (1.5, 1.4 GHz)
Level Two cache: 256 KB Advanced
Transfer Cache (Integrated)
System Bus Speed: 400 MHz
SSE2 SIMD Extensions
Transistors: 42 Million
Typical Use: Desktops and entrylevel workstations

EE414 VLSI Design

Pentium 4
0.13-micron

process technology
(2.53, 2.2, 2 GHz)
Introduction date: January 7, 2002
Level Two cache: 512 KB Advanced
Transistors: 55 Million

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Intels McKinley

Introduction date: Mid

2002
Caches: 32KB L1,
256 KB L2, 3MB L3 (onchip)
Clock: 1GHz
Transistors: 221 Million
Area: 464mm2
Typical Use:
High-end servers
Future versions:
5GHz, 0.13-micron
technology

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Evolution of Electronics

EE414 VLSI Design

Moores Law
IIn

1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 12 months.
HHe made a prediction that
semiconductor technology will double its
effectiveness every 18 months

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LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION

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16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Electronics, April 19, 1965.

1975

1974

1973

1972

1971

1970

1969

1968

1967

1966

1965

1964

1963

1962

1961

1960

1959

Moores Law

Evolution in Complexity

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Transistor Counts
1 Billion
Transistors

K
1,000,000
100,000
10,000
1,000
i386
80286

100
10

i486

Pentium III
Pentium II
Pentium Pro
Pentium

8086
Source: Intel

1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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Courtesy, Intel

Moores law in
Microprocessors

Transistors (MT)

1000

2X growth in 1.96 years!

100
10

486

1
386
286

0.1
0.01

P6
Pentium proc

8086
8080
8008
4004

8085

0.001
1970

1980

1990
Year

2000

2010

Transistors on Lead Microprocessors double every 2 years

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Courtesy, Intel

Die Size Growth

Die size (mm)

100

10
8080
8008
4004

8086
8085

286

386

P6
Pentium
proc
486

~7% growth per year

~2X growth in 10 years

1
1970

1980

1990
Year

2000

2010

Die size grows by 14% to satisfy Moores Law

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Courtesy, Intel

Frequency

Frequency (Mhz)

10000

Doubles every
2 years

1000
100
10

8085

1
0.1
1970

8086 286

386

486

P6
Pentium proc

8080
8008
4004
1980

1990
Year

2000

2010

Lead Microprocessors frequency doubles every 2 years

EE414 VLSI Design

Courtesy, Intel

Power Dissipation

Power (Watts)

100
P6
Pentium proc
10
8086 286
1

8008
4004

486
386

8085
8080

0.1
1971

1974

1978

1985

1992

2000

Year

Lead Microprocessors power continues to increase

EE414 VLSI Design

Courtesy, Intel

Power will be a major

problem
100000

18KW
5KW
1.5KW
500W

Power (Watts)

10000
1000

Pentium proc

100

286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

EE414 VLSI Design

Courtesy, Intel

Power density
Power Density (W/cm2)

10000

Rocket
Nozzle

1000

Nuclear
Reactor

100
8086

10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year

Power density too high to keep junctions at low temp

EE414 VLSI Design

Courtesy, Intel

Not Only Microprocessors

Cell
Phone
Small
Signal RF

Digital Cellular Market

(Phones Shipped)

1996 1997 1998 1999 2000

Units

48M 86M 162M 260M 435M

(data from Texas Instruments)

EE414 VLSI Design

Power
RF

Power
Management

Analog
Baseband
Digital Baseband
(DSP + MCU)

Challenges in Digital Design

Microscopic Problems
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.
Everything Looks a Little Different

EE414 VLSI Design

Macroscopic Issues
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.
and Theres a Lot of Them!

10,000
10,000,000

100,000
100,000,000

Logic Tr./Chip
Tr./Staff Month.

Complexity

1,000
1,000,000

10,000
10,000,000

100
100,000

Productivity
(K) Trans./Staff - Mo.

Logic Transistor per Chip (M)

Productivity Trends

1,000
1,000,000
58%/Yr. compounded
Complexity growth rate

10
10,000

100
100,000

1,0001

10
10,000
x

0.1
100

xx

0.01
10

xx
x

1
1,000

21%/Yr. compound
Productivity growth rate

0.1
100
0.01
10

2009

2007

2005

2003

2001

1999

1997

1995

1993

1991

1989

1987

1985

1983

1981

0.001
1

Source: Sematech

Complexity outpaces design productivity

EE414 VLSI Design

Courtesy, ITRS Roadmap

Why Scaling?

Technology shrinks by 0.7/generation

With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
How to design chips with more and more functions?
Design engineering population does not double every
two years

Hence, a need for more efficient design methods

Exploit different levels of abstraction

EE414 VLSI Design

Design Abstraction Levels

SYSTEM

MODULE
+
GATE

CIRCUIT

DEVICE
G
S
n+
EE414 VLSI Design

D
n+

Design Metrics

How to evaluate performance of a

digital circuit (gate, block, )?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function

EE414 VLSI Design

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs

design time and effort, mask generation
one-time cost factor

Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

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NRE Cost is Increasing

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Die Cost
Single die

Wafer

Going up to 12 (30cm
From http://www.amd.com

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Cost per Transistor

cost:

-per-transistor

1
0.1

Fabrication capital cost per transistor (Moores law)

0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982

1985

EE414 VLSI Design

1988

1991

1994

1997

2000

2003

2006

2009

2012

Yield
No. of good chips per wafer
Y
100%
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield

wafer diameter/2 2 wafer diameter

Dies per wafer

die area
2 die area

EE414 VLSI Design

Defects

defects per unit area die area

die yield 1

is approximately 3
die cost f (die area)4
EE414 VLSI Design

Some Examples (1994)

Chip

Metal Line
layers width

Wafer
cost

Def./ Area Dies/ Yield

cm2 mm2 wafer

Die
cost

386DX

0.90

$900

1.0

43

360

71%

$4

486 DX2

0.80

$1200

1.0

81

181

54%

$12

Power PC
601

0.80

$1700

1.3

121

115

28%

$53

HP PA 7100

0.80

$1300

1.0

196

66

27%

$73

DEC Alpha

0.70

$1500

1.2

234

53

19%

$149

Super Sparc

0.70

$1700

1.6

256

48

13%

$272

Pentium

0.80

$1500

1.5

296

40

9%

$417

EE414 VLSI Design

Reliability
Noise in Digital Integrated Circuits

v(t)

VDD

i(t)

(a) Inductive coupling

(b) Capacitive coupling

(c) Power and ground

noise

EE414 VLSI Design

DC Operation
Voltage Transfer Characteristic
V(y)

VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)

OH

V(y)=V(x)

VM Switching Threshold
VOL

VOL

OH

V(x)

Nominal Voltage Levels

EE414 VLSI Design

Mapping between analog and digital

signals

"1"

OH
V
IH

V(y)
Slope = -1

V
OH

Undefined
Region

"0"

V
IL
V
OL

EE414 VLSI Design

Slope = -1
VOL
V

IL

IH

V(x)

Definition of Noise Margins

"1"
V

OH

NMH

Noise margin high

IH
Undefined
Region

V
OL

NML

IL

"0"
Gate Output

EE414 VLSI Design

Gate Input

Noise margin low

Noise Budget
Allocates gross noise margin to
expected sources of noise
Sources: supply noise, cross talk,
interference, offset
Differentiate between fixed and
proportional noise sources

EE414 VLSI Design

Key Reliability Properties

Absolute noise margin values are deceptive

a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)

Noise immunity is the more important metric

the capability to suppress noise sources

Key metrics: Noise transfer functions, Output

impedance of the driver and input impedance of the

receiver;
EE414 VLSI Design

Regenerative Property
out
v3

out
finv (v)

f(v)

v1

v1
v3

finv(v)

v2

v0

Regenerative
EE414 VLSI Design

in

f(v)

v0

v2

in

Non-Regenerative

Regenerative Property

v0

v1

v2

v3

v4

v5

(a) A chain of inverters

V (Volt)

5
v0

v1

(b) Simulated response of

chain of MOS inverters

6
t (nsec)

EE414 VLSI Design

v2

10

v6

Fan-in and Fan-out

(a) Fan-out N

M
N

EE414 VLSI Design

(b) Fan-in M

The Ideal Gate

Vout

Ri =
Ro = 0
g=

Fanout =
Vin

EE414 VLSI Design

NMH = NML = VDD/2

An Old-time Inverter
5.0

V ou t (V)

4.0

NML

3.0
2.0

VM

1.0

0.0

EE414 VLSI Design

1.0

2.0

NMH

3.0
Vi n (V)

4.0

5.0

Delay Definitions
Vin

50%
t
Vout

tpHL

tpLH
90%
50%
10%

tf
EE414 VLSI Design

tr

Ring Oscillator
v

T = 2 tp N
EE414 VLSI Design

A First-Order RC Network
R

vin

vout
C

tp = ln (2) = 0.69 RC

Important model matches delay of inverter

EE414 VLSI Design

Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t T
1 t T
Pave
p (t )dt
isupply t dt

t
T t
T
EE414 VLSI Design

Energy and Energy-Delay

Power-Delay Product (PDP) =
E = Energy per operation = Pav tp
Energy-Delay Product (EDP) =
quality metric of gate = E tp

EE414 VLSI Design

A First-Order RC Network
Vdd

E0>1=C LVdd2

A1
AN
vin

R PMOS

NETWORKvout
NMOS CL

isupply

Vout

CL

NETWORK
Vdd
T
T
E 0 1 = P t dt = V dd i sup ply t dt = Vdd CL dV out = C L V dd 2
0
0
0
T
T
Vdd
1
2
E ca p = P cap t dt = V out i ca p t dt = C L Vout dVout = C V dd
2 L
0
0
0
EE414 VLSI Design

Summary

Digital integrated circuits have come a long

way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and
potential solutions is the purpose of this book

Understanding the design metrics that govern

digital design is crucial
Cost, reliability, speed, power and energy
dissipation

EE414 VLSI Design