Counter Circuits and

Applications
Group 6

Overview
Analysis of Sequential Circuits.
Ripple Counters.
Design of Divide-by-N Counters.
Ripple Counter ICs.
Applications.
System Design Applications.
Seven-Segment LED Display Decoders.

Synchronous Counters.
Synchronous Up/Down-Counter ICs.
Applications.

Analysis of Sequential
Circuits
Using Timing Diagrams to analyze.

Ripple Counters
J-K flip-flops are in the toggle mode.
Output Q is cascaded to the next clock
input.

Ripple Counters(contd)
Ideal Timing Diagram.

Ripple Counters(contd)
Ripple: the input clock trigger isnt
connected to each flip-flop directly but
propagate thru all the flip-flops. Nonideal Timing Diagram:

Ripple Counters(contd)
Down counter:

Design of Divide-by-N
Counters
An example of MOD-5 counter.

Design of Divide-by-N
Counters (contd)
Glitch effect: NAND propagation time
15ns & Flip-flop Reseting time 30ns (For
74LS76 and 7400).

Design of Divide-by-N
Counters (contd)
MOD-5 counter which counts in the
sequence 6-7-8-9-10-6-7-8-9-10-,etc.

Ripple Counter ICs - 7493

7493: a divide-by-2 and a divide-by-8
MR1,MR2 can be utilized to do MOD-N.

Ripple Counter ICs 7493

(contd)
External connection as a MOD-16
counter.

Ripple Counter ICs 7493

(contd)
External connection as a MOD-12
counter.

Ripple Counter ICs 7490

7490: a divide-by-2 and a divideby-5.
01

01

01

Ripple Counter ICs - 7492

7492: a divide-by-2 and a divideby-6.
01

10

01

System Design Application

A 3-digit decimal counter (000

999)
When the count changes from (1001) to
(0000), the 23 output line goes from
HIGH to LOW and trigger the next
counter.

Seven-Segment LED
Display Decoders
7447: the most popular common-anode
decoder. It has a lamp test (LT) input
for testing all segments, and it also has
ripple blanking input and output
(RBI,RBO).

Synchronous Counters
Synchronous counters eliminate the
propagation delay problem because all
the clock inputs (cp) are tied to a
common clock.

Synchronous
Counters(contd)
A MOD-6 synchronous binary upcounter.

Synchronous Up/DownCounter ICs

MR(Master
Reset):
anD
active-HIGH
Reset
for
When
TCDU(normally
HIGH)
PL(Parallel
Two
separate
Load)
clock
&
inputs:
place
CpU for
anyLOW,
0~D3: becomes
resetting
the
outputs
to, zero.
binary
counting
value
up
and
on
DC0pD
~Dfor
counting
and
down.
the
it
is used
to Q
indicate
that
thedrive
maximum
minimum
3
count
isLOW.
reached
and
theHIGH
countwhile
is about
PL
One
line
clock
must be
held
to
recyclewith
to the
zero(carry
counting
themaximum(borrow
other.condition). It
can be usedItas
condition).
can
thebe
next
used
stage
as the
of a
next
multistage
stage
of a multistage
counter. counter.

Applications of
Synchronous Counter ICs
A divide-by-200 using synchronous
counters.
Parallel Load Value
200

Borrow
Condition