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Sigma-Delta ADC
Sigma-delta ADCs consist of a sigma-delta modulator followed by
a digital filter. The modulator continuously samples the analog
input at a high sampling rate and outputs a 1-bit data stream.
The quantity of ones in the bit stream corresponds to the analog
input voltage. The digital filter then processes the bit stream and
performs decimation to generate the 24-bit conversion.
Sinc3 filters are used as the digital filters. The output data rate,
fADC, which is the rate at which the ADC continuously converts
on a single channel, is equal to
RS-485 Format :
For handling the requirements of 48 channels (3 groups of 16 channels) are
catered by 3 PIC18F6520 microcontrollers.
RS-485 (a telecommunication standard for binary serial communications
between devices) is used for communication between DAU and DPU.
Command from DPU consists of a start bit which is low, 8 message bits
indicating the channel number, a high mode bit indicating command and
stop bit which is high.
With a baud rate of 2MBPS, this command of 11 bits require 5.5s.
Once the command is received, the microcontroller decodes it, verifies if the
channel number requested lies within the range of channels addressed by it.
The microcontroller then fetches the data from the corresponding memory
location and puts it back on the RS- 485 link as two words.
The DPU issues command once in every 32 s and the reply from DAU is
posted in that 32s interval. This is illustrated in figure.
Procedure:
Apply a sinusoidal signal of amplitude of (V max-Vmin)/2 from the AC source.
Vary the input frequency by 0.0262Fs ,0.262Fs ,0.7850Fs , Fs , 1.150Fs .
(Fs Datarate of channel in Hz) and measure output voltage.
Calculate the required gain and verify with the expected response.
Pass-Fail Criteria :
At cut-off frequency, gain should be within the range of -2.97 and -3.03dB.
Notch frequency gain and First Side Lobe gain should be less than -40 dB.
Expected Response :
1
2
3
5
Thank You