8086 SYSTEM

CONNECTIONS and TIMING

8086 Pin Diagram

CPU: Instruction Cycle

Three basic operations:

Fetch: fetches the instruction, copying it from memory into the

instruction queue, and increments the PC (program counter)

Decode: control unit determines the type of the instruction.

Retrieves any needed operands and sends them to the ALU. Also
sends the ALU signals to indicate the type of operation.

Execute: ALU executes the instruction,

returns output to the destination, and
update the status flags.

Each step takes one click of the System clock: one clock cycle.

Basic Terms in Timing

CLK is divided into States.

Machine cycle:

Time taken for Reading or Writing a byte with

Memory or Port.
Machine cycle consists of many states.

Instruction Cycle:

Time taken for fetch,decode,excute an

Instruction.
Instruction Cycle consists of many Machine
Cycles.

Pin Description

AD0-AD15: Multiplexed Address/Data Bus

RD: Low while reading from memory or port

WR : Low while writing to memory or port.

M/IO : High during Memory operations.

Low during Port operations.

ALE : High to enable Address Latches.

S0-S2 Bus Control, INTA, I/O read, I/O write, HALT, code
access, memory read, memory write, release bus.

S3-S6, QS0-QS1: Status of internal state

Pin Description (Contd)

BHE:

Combines with A0 to form the operation for transfer of Address

Reset:

Causes the processor to immediately terminate its present

activity and restarts execution again.

Ready:

DEN:

When CPU asks for a byte from memory, memory is expected to deliver
within 4 bus cycles. If memory is too slow, it negates Ready and keeps it
negated until the byte is put on the bus.
Output enable for the Data Transceiver.

DT/R:

It is used to control the direction of data flow through the transceiver (T =

1, R =0).

Fetching an instruction:

CPU puts the address of the instruction

on the address pins
Asserts memory read
Memory replies by putting instruction
on data pins
Asserts a signal that its done (READY)
When CPU sees the signal, it accepts
the word and carries out the
instruction

Read Machine Cycle

Asserts M/IO for reading from Memory or Port.

Asserts ALE High to enable Address Latches.
Sends desired address on A0-A19 pins.
Asserts ALE Low to latch address on external
latches.
Removes the address from A0-A19
Asserts RD Low to output data into data bus.
Assets READY Low to send 8086 into wait
state.

Read Machine Cycle

(Contd..)

In Wait State, 8086 will wait for addressed

memory or port to output data.
Asserts Ready High to specify that addressed
memory or port has placed data on data bus.
DT/R is Low to specify that 8086 is receiving
the data.
DEN is Low to enable data buffers for
transfer data from addressed memory or
port to 8086.

Write Machine Cycle

Asserts M/IO for writing from Memory or Port.

Asserts ALE High to enable Address Latches.
Sends desired address on A0-A19 pins.
Asserts ALE Low to latch address on external
latches.
Removes the address from A0-A19
Asserts WR Low to output data into data bus.
Assets READY Low to send 8086 into wait state.

Write Machine Cycle

(Contd..)

In Wait State, 8086 will wait for addressed

memory or port to receive data.
Asserts Ready High to specify that
addressed memory or port is ready to
receive data on data bus.
DT/R is High to specify that 8086 is
transmitting the data.
DEN is Low to enable data buffers for
transfer of data from 8086 to addressed
memory or port .

Minimum & Maximum

Mode

Minimum Mode:

MN/MX = 1

Processor produces the Control Bus Signals.

WR,M/IO, DT/R, DEN, ALE, INTA will be accessed.

Maximum Mode:

MN/MX = 0

External device produces the control bus signals.

S0,S1, S2, QS0, QS1, LOCK will be accessed.

Maximum Mode system

Timing diagrams for Maximum Mode

system

The S0, S1 and S2 bits are set just prior to beginning of bus cycle.
Then the 8288 will output a pulse on its ALE and apply appropriate
signal to DT/R during T1
In T2 8288 will set DEN = 1 , thus it enables Tran receivers and for
input it will activate either MRDC or IORC.
For output it will activate either AMWC or AIOWC is activated from
and MWTC or IOWC is activated from T3 to T4.

It is a series of three pulses shown in fig.

The request grant pins are checked at each rising edge of clock

When a request is detected the processor issues a grant pulse over the RQ/G
Immediately during T4 of current or T1 of next state

INTERRUPTS
And Interrupt
Responses

INTRODUCTION

Interrupt is a request to microprocessor.

While executing a normal program, if an interrupt

occurs, microprocessor will stop the current
program and services the interrupt.

Servicing the interrupt means, it will execute the

interrupt service procedure (Procedure for that
interrupt).

An IRET instruction at the end of interrupt service

procedure will return to the executing program.

Sources of Interrupts

Hardware Interrupt:

Software Interrupt:

External Signal applied to NMI (NonMaskable Interrupt) or INTR (Interrupt) Pin.

Execution of Interrupt Instruction INT.

Error Condition:

Error occurred while executing an

instruction.
ex: Dividing an operand by 0.

8086 Response to
Interrupt

DEC SP by 2 and pushes FW

(Flag word) on the stack.
Clears IF (Interrupt Flag) to
disables 8086 INTR input.
Resets trap flag in the flag
register.
DEC SP by 2 and pushes CS
register.
DEC SP by 2 and pushes IP
register.
It performs Indirect Far
Jump to start Interrupt
Service Procedure.

Interrupt Pointer Table

The starting address of ISP is known as Interrupt

vector or Interrupt Pointer.
In 8086 Memory, the 1st KB i.e. 00000-003FF is set
aside for storing 256 interrupt pointers.
This 1KB of memory is called Interrupt Pointer
Tables.
IP Value is kept as low word.
CS Value is kept as high word.
Each Double Word is assigned a number from 0 to
255, which is called Type.
Lowest 5 types i.e. are specified interrupts.

Interrupt Pointer Table

(Contd..)

Type0 Divide Error.

Type1 Single Step.
Type2 Non-Maskable.
Type3 INT Instruction.
Type4 Overflow
Type 5-31 Reserved
Interrupt Pointers.
Type 31-255 Available
Hardware and Software
User Interrupts.

Type-0 Interrupt Pointer

It is a Divide by zero Interrupt.

It is generated when the result of DIV or IDIV
operation is too large to fit in destination
register.
Processor responses to Type-0 pointer same as
for all interrupts.
It gets the starting address of the Type-0 ISP
from 00000-000003 Location.
i.e. CS from 00002,000003 address.
IP from 00001,00000 address.
IRET is used to return to interrupted program.

Type-1 Interrupt Pointer

It is a Single Step Interrupt.

It will execute each Instruction and
stops for the user to examine the
contents of Registers, Memory locations.
When Trap Flag is set, then Type 1
Interrupt is generated.
It gets CS of ISP from 00006H and IP 00004H.

Type-2 Interrupt Pointer

It is a Non-Maskable Interrupt.
Type-2 Interrupt cannot be disabled by
Program Instructions.
When a low to high transition is received on
NMI pin,Type-2 Interrupt is Generated.
It gets CS of ISP from 0000AH and IP 00008H.
Ex: When there is a power failure, an interrupt
is sent to NMI pin to save the program data.

Type-3 Interrupt Pointer

It is a Breakpoint Interrupt, which is produced

by INT 3 Instruction.
When we insert a Breakpoint in the program,
execution is done upto the breakpoint and
then goes to breakpoint procedure.
Usually Breakpoint Procedure displays the
register values and wait for command from
the user.
It gets CS of ISP from 0000EH and IP
0000CH.

Type-4 Interrupt Pointer

It is a Overflow Interrupt, which is occurred when

Overflow Flag is set.
OF is set when arithmetic operation of two signed
numbers is too large to represent in destination register.
This overflow error is detected and responded using
INTO Instruction.
If OF=0, then INTO is treated as NOP.
If OF=1, then Interrupt is generated and It gets CS of
ISP from 00012H and IP - 00010H.
The advantage of this interrupt is that the ISP can be
easily accessed from any program.

Software Interrupts

INT Instruction can be used to specify the

Interrupt Types 0 255.

INT 0 is for generating Type 0 Interrupt

without dividing the operand by ZERO.

Similarly INT 3 is Breakpoint Interrupt (Type

3).

INT 32 to INT 255 are user defined

Interrupts.

INTR Interrupts

INTR allows some external signal to interrupt

execution of a program.
This INTR Interrupt is masked interrupt, which can
be disabled by clearing IF (Interrupt Flag) using CLI
(Clear Interrupt) instruction.
The INTR input can be enabled by setting IF using
STI (Set Interrupt) instruction.
8086 responds differently to an INTR Interrupt.
The interrupt type is sent to 8086 from an external
device such as 8259A (Priority Interrupt Controller).

Interrupt Instructions

Priority of Interrupts

The Priority of the interrupts is in the following

order:

Internal Interrupts and Exceptions (Highest Priority)

Software Interrupts (INT 0 to INT 255) .

Non Maskable Interrupt. (Exception for priority).

Hardware Interrupt INTR (Lowest priority).

The Lowest the Type No. the highest is the priority.

Type0 has highest and Type255 has lowest priority.