Professional Documents
Culture Documents
Dr. T. R. Lenka
Asst. Professor
Deptt. of Electronics & Communication Engg.
National Institute of Technology Silchar
VLSI Design
VLSI Design
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
VLSI Design
VLSI Design
First transistor
Bell Labs, 1948
VLSI Design
Evolution of Microelectronics
1948
1961
1966
1971
1980
Discrete
Component
SSI
MSI
LSI
VLSI
1
transistor
100
100-1000
1000-20000
>20000
Gates, Counters,
MUX,
FFs
Adders
VLSI Design
8-bit uP,
ROM, RAM
Complex
uP, SoC
VLSI Design
2002
42 million transistors
3GHz operation
VLSI Design
Moores Law
In
VLSI Design
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLSI Design
1975
1974
1973
1972
1971
1970
1969
1968
1967
1966
1965
1964
1963
1962
1961
1960
1959
Moores Law
Evolution in Complexity
VLSI Design
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i386
80286
100
10
i486
Pentium III
Pentium II
Pentium Pro
Pentium
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
VLSI Design
Courtesy,
Intel
Transistors (MT)
1000
100
10
486
P6
Pentium proc
386
286
0.1
8086
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
8080
8008
4004
0.001
1970
1980
1990
Year
Courtesy, Intel
VLSI Design
2000
2010
100
10
8080
8008
4004
8086
8085
286
386
P6
Pentium
proc
486
1
1970
1980
1990
Year
2000
2010
VLSI Design
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
10
8085
1
0.1
1970
8086 286
386
486
P6
Pentium proc
8080
8008
4004
1980
1990
Year
2000
2010
Power Dissipation
Power (Watts)
100
P6
Pentium proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium proc
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
VLSI Design
Courtesy,
Intel
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power
RF
Power
Management
Analog
Baseband
Digital Baseband
(DSP + MCU)
Microscopic Problems
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse : Portability
Predictability.
VLSI Design
Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
Design Metrics
How
to evaluate performance of a
digital circuit (gate, block, )?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
VLSI Design
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
VLSI Design
D
n+
Silicon Wafer
Single die
Wafer
Going up to 12 (30cm
From http://www.amd.com
VLSI Design
Design Flow
Design Iteration
Design Capture
Behavioral
HDL
HDL
Pre-Layout
Pre-Layout
Simulation
Simulation
Logic
LogicSynthesis
Synthesis
Post-Layout
Post-Layout
Simulation
Simulation
Circuit
CircuitExtraction
Extraction
Floorplanning
Floorplanning
Placement
Placement
Routing
Routing
Tape-out
VLSI Design
Structural or
Gate level
Physical
Netlist with
Place-and-Route Info
Place-and-Route
Place-and-Route
Optimization
Optimization
VLSI Design Artwork
Design Methodology
A Simple Processor
INPUT/OUTPUT
MEMORY
CONTROL
DATAPATH
VLSI Design
A System-on-a-Chip: Example
Courtesy: Philips
VLSI Design
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
Array-based
Macro Cells
Pre-diffused
(Gate Arrays)
VLSI Design
Pre-wired
(FPGA's)
VLSI Design
Courtesy
Intel
Intel 8080
Intel 8286
VLSI Design
Courtesy
Intel
Intel 8085
Intel 8486
Rows of cells
Feedthrough cell
Logic cell
Routing
channel
Functional
module
(RAM,
multiplier,)
VLSI Design
Routing channel
requirements are
reduced by presence
of more interconnect
layers
VLSI Design
VLSI Design
MacroModules
VLSI Design
Soft macros
VLSI Design
Firm macros
Firm
VLSI Design
Hard macro
Hard macros are generally in the form of hardware IPs (or we termed it
as hardwre IPs !).
Hard macos are targeted for specific IC manufacturing technology.
Hard macros are block level designs which are silicon tested and
proved.
Hard macros have been optimized for power or area or timing.
In physical design you can only access pins of hard macros unlike soft
macros which allows us to manipulate in different way.
You have freedom to move, rotate, flip but you can't touch anything
inside hard macros.
Very common example of hard macro is memory. It can be any design
which carries dedicated single functionality (in general).. for example it
can be a MP4 decoder.
Be aware of features and characteristics of hard macro before you use it
in your design... other than power, timing and area you also should know
pin properties like sync pin, I/O standards etc
LEF, GDS2 file format allows easy usage of macros in different tools.
VLSI Design
VLSI Design
Soft MacroModules
Synopsys DesignCompiler
VLSI Design
Intellectual Property
Hard macro, firm macro and soft macro are all known
as IP (Intellectual property).
They are optimized for power, area and performance.
They can be purchased and used in your ASIC or
FPGA design implementation flow.
Soft macro is flexible for all type of ASIC
implementation.
Hard macro can be used in pure ASIC design flow, not
in FPGA flow.
Before bying any IP it is very important to evaluate its
advantages and disadvantages over each other,
hardware compatibility such as I/O standards with
your design blocks, reusability for other designs.
VLSI Design
Late-Binding Implementation
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
VLSI Design
rowsof
uncommitted
cells
metal
possible
contact
GND
In 1 In2
In 3 In4
routing
channel
Committed
Cell
(4-input NOR)
Out
VLSI Design
Uncommited
Cell
Sea-of-gates
Random Logic
Memory
Subsystem
LSI Logic LEA300K
(0.6 m CMOS)
VLSI Design
Courtesy
LSI Logic
Prewired Arrays
Classification of prewired arrays (or field-programmable devices):
VLSI Design
Volatile FPGA
(EPLDs)
RAM
Based FPGA
Array logic +
Embedded EPROM
Cell logic +
Embedded RAM
Serial PROM
VLSI Design
Cell
based logic
I4
I3
I2
I1
I0
Programmable
OR array
I2
I1
I0
Programmable
OR array
PLA
I3
I5
I4
I3
I2
I1
I0
Fixed OR array
PROM
Indicates programmable connection
Indicates fixed connection
VLSI Design
O 3O 2O 1 O 0
PAL
Programming a PROM
1
X2
X1
X0
: programmed node
NA NA f 1 f 0
VLSI Design
Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)
minterm
GND
GND
V DD
GND
GND
GND
GND
V DD
X0
X0
X1
X1
X2
X2
AND-plane
f0
f1
OR-plane
VLSI Design
k macrocells
product
terms
j -wide OR array
D
OUT
j
macrocell
CLK
A
i inputs
VLSI Design
0
F
F = AS + BS
VLSI Design
F=
0
0
0
0
X
Y
Y
1
1
1
0
X
Y
Y
0
0
1
0
0
1
0
1
1
X
Y
X
X
X
Y
1
0
X
Y
XY
XY
XY
X+ Y
X
Y
1
SA
Y
1
C
D
SB
S0
S1
VLSI Design
Memory
ln1 ln2
In
Out
00
00
0
01
10
11
C1....C4
H1
G4
G3
G2
Logic
function
of
G1-G4
G1
F3
F2
F1
Logic
function
of
F1-F4
K
CLOCK
SR/H0 EC
Bits
control
Din
Logic
function
of
F,G, H1
F4
DIN/H2
Bypass
F
G
H
D SD Q
G
H
EC RD
1
Y
Bits
control
Din
F
G
H
YQ
D SD Q
Bypass
XQ
EC RD
H
F
1
Multiplexer Controlled
by Configuration Program
Courtesy Xilinx
VLSI Design
Programmable Interconnection
M
Interconnect
Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
VLSI Design
CLB
CLB
CLB
Connect Box
CLB
CLB
CLB
Interconnect
Point
CLB
CLB
Design
CourtesyVLSI
Dehon
and Wawrzyniek
Design
CourtesyVLSI
Dehon
and Wawrzyniek
Primary inputs
Courtesy Altera
VLSI Design
CLB
12
Quad
Single
Double
Long
2
3
12
Quad
Long
Global
Long
Clock
2
Carry
Direct
VLSI Design
Courtesy
Xilinx
Direct
Connect
Long
Design at a crossroad
Analog
System-on-a-Chip
C
system
+2 Gbit
DRAM
Recognition
VLSI Design
Embedded applications
where cost, performance,
and energy are the real
issues!
DSP and control intensive
Mixed-mode
Combines programmable
and application-specific
modules
Software plays crucial role
Reuse element
Status
1st
Standard cells
Well established
2nd
IP blocks
Being introduced
3rd
Architecture
Emerging
4th
IC
Early research
VLSI Design
Embedded memories
Embedded PowerPc
Hardwired multipliers
High-speed I/O
VLSI Design
ASIC
Expensive
Flexibility
Good
Limited
Programming
by customer
Full
Limited
hardware
change
VLSI Design
Good in terms of
speed, area and
power consumption
VLSI Testing
VLSI Design
N inputs
N inputs
K Outputs
M stage
Combinational
K Outputs
M stage
Register
Sequential
VLSI Design