VHSIC: Very High Speed Integrated

Circuits.

Used to describe the structure &

behavior of a digital system.

VHDL established to IEEE standard in

1987.

It is used for high speed integrated ckt

design.

Package
Entity
Architecture
Entity
Archr
Pair

Entity
Archr
Pair

Entity
Archr
Pair

Configuration

For Declaring all the i/p, o/p signals in a

digital circuit.

Entity gives interfacing between device &

the other peripherals.

An entity has one or more ports which

are analogous to the pins on a schematic
symbol.

All the information must flow into & out

of the entity through the ports.

Each port must contain name, data flow

direction & type.

Entity <entity_name> is
port( <signal_name1>: <mode> <type>;
<signal_name2>: <mode> <type>;
--);
End <entity_name>;
Where
Entity name : identifier selected by the user
Signal name: name of the external interface signal
Modes:
IN: Input port
OUT: Output port
INOUT: Bidirectional port
Buffer: Output port

Entity ful_adder is
port( A, B, Cin : IN BIT;
Sum, Cout : OUT BIT);
End ful_adder;
Entity declaration for: 4-to-1 mux
Entity mux_4_1 is
port( D : IN BIT_VECTOR(0 to 3);
S1, S0 : OUT BIT;
Y : OUT BIT);
End mux_4_1;

The internal details of an entity are

specified by an Architecture using one of
the following modeling styles:
1.Structural modeling
2. Dataflow modeling
3. Behavioral modeling

Architecture specifies behavior,

functionality, interconnections or
relationship between inputs & outputs.

It is the actual description of the design.

An architecture consist of 2 parts:
1. Arch. Declaration
2. Arch. Body

Architecture <arch_name> of <entity_name> is

[ <arch_declarations>]
Begin
<archi_statemements>
End <arch_name>

An entity can have more than one architecture

but there can be no architecture without an entity.

Library: Can be System or User library

Ex. Of system library: IEEE library.

Library clause: to visible logical names of libraries

Syntax:
LIBRARY <list of logical library names>;
for ex. LIBRARY IEEE;

USE clause: it imports all the declarations within the

package.
Syntax :
USE <library_name>. <primary unit_name>
Ex1: LIBRARY TTL
USE TTL.NOR1;
Ex2: LIBRARY IEEE
USE IEEE.STD_LOGIC_VECTOR. STD_LOGIC.
Ex3: USE IEEE.STD_LOGIC_VECTOR.ALL

Logical
Relational
Arithmetic
Shift and Rotate

VHDL data types:

Scalar/ discrete types

Composite types
Access types
File types
Other types

It includes:
Numeric data types: integer, floating point
(real)
Enumerated types: BIT, Boolean, & character
User defined types: user can define a type by
using keyword: TYPE
Ex: TYPE arth_op is ( add, sub, mul, div);

It includes:
Array : 1) string 2) Bit_vector
Records: it is analogous to struct in C
Ex:
Type DATE is
record
day: Integer range 1 to 31
month: mth_name;
year: integer range 0 to 4000;
End record;

There are several other types provided by

external library IEEE.
These library contains a std_logic_1164
package which supports more types.
std_logic type:
Defined by IEEE std 1164
Defined in the file ieee.vhd.std_logic
It is an enumerated type with one of the 9 values:
U, X, 0,1, Z, W, L, H, -

It represents an Array of Bits whose type is

std_logic.
Ex:
port (I: IN std_logic_vector ( 7 downto 0);
O: OUT Bit);

Port I is declared as type std_logic_vector

with 8 bits.

1)

Signal: it represents a wire signal in a ckt.

Syntax:
signal <signal_name> :
<type_name>;
Ex:
Signal X: BIT
Signal can be placed at any of the
following 3 places:
1) An entity declaration
2) Arch declaration section
3) Package declaration section

2) Variable:
Unlike signal a variable does not necessarily
represents a wire in a ckt.
Syntax:
Variable var_name: var_type:= initial_value.
Ex: variable index: Integer range 0 to 20:= 0;
3) Constants:
Syntax:
constant const_name: type:= value;
Ex:
constant Bus_size: Integer:= 32

There are different ways of describing

combinational ckts in VHDL
These alternatives are based on the
modeling styles used for describing a ckt.
The internal details of an entity are
specified by an Architecture using one of
the following modeling styles:
1. Structural modeling/Gate level
modeling
2. Dataflow modeling
3. Behavioral modeling

An Architecture that uses components.

In this Archi has 2 parts:

Declarative parts (Before begin):

Component instantiation (after begin)

Declarative parts:
All different components used in the system
description are declared.
For ex. Description of AND gate components:
Component AND2
port ( I1, I2: IN STD_LOGIC;
O2: OUT STD_LOGIC);
End component

Syntax:
Comp_label: comp_name port map
( signal1, signal2 signaln );
Ex:
A2: and2 port map (A,B, Cout);

Means the logic relationship between A,

B & Cout is same as between I1, I2 &
O1.

VHDL Code:

Library IEEE;
USE IEEE.std_logic_1164.all;
-- Entity declaration
Entity half_adder is
port( A, B, : IN std_logic;
Sum, Cout : OUT std_logic);
End half_adder;
Continue..

Architecture adder of half_adder is

-- Component declaration
Component XOR2
Port (I1,I2: IN std_logic;
o1: OUT std_logic);
End component;
Component AND2
Port (I1,I2: IN std_logic;
o1: OUT std_logic);
End component;
Continue..

Begin
-- Component instantiation
X1: XOR2 port map (A, B, Sum)
A1: AND2 port map (A,B, Cout)
End Adder

Library IEEE;
USE IEEE.std_logic_1164.all
Entity XOR2 is
port (I1, I2: IN std_logic;
O1: OUT std_logic);
End XOR2;
Architecture XOR_gate of XOR2 is
Begin
O1 I1 XOR I2;
End XOR_gate;

Library IEEE;
USE IEEE.std_logic_1164.all
Entity AND2 is
port (I1, I2: IN std_logic;
O1: OUT std_logic);
End AND2;
Architecture AND_gate of AND2 is
Begin
O1 I1 AND I2;
End AND_gate;

Concurrent signal assignment statements

are used in this modeling style.
Full adder equations are:

Sum= ABC;
Cout= AB + AC + BC;
Which can be represented using dataflow
modeling having concurrent stmts as:
Sum A XOR B XOR C
after 10ns;
Cout (A AND B) OR ( A AND C) OR (B AND C) after
20ns;

Following conditional signal assignment

stmts can be used in the dataflow modeling:
WHEN-ELSE stmt:
Syntax:
<expn1> WHEN <Cond> ELSE <expn2>;
Exs: 1) x 1 WHEN b<= c ELSE 0;
2) y j WHEN x=0 ELSE
k WHEN x=1 ELSE
m WHEN OTHERS;

With select_expn select

target_signal expn1 when choices;
expn2 when choices;
--Ex:
with select_lines select
Y
I0 when 00;
I1 when 01;
I2 when 10;
I3 when 11;

Entity f_adder is
port( A, B, Cin : IN bit;
Sum, Cout : OUT bit);
End f_adder;
Architecture adder of f_adder is
Begin
sum A XOR B XOR Cin;
Cout (A and B) OR ( Cin and A) Or
( Cin
And B);
End adder;