8085 PIN DIAGRAM &

SIGNALS

8085 STATUS & CONTROL

SIGNALS

8085ARCHITECTURE/BLOCK
DIAGRAM

8085 ADDRESSING MODES

The method of specifying the data to be operated by the

instruction is called Addressing

Immediate Addressing
Data is specified in the instruction itself
EX. MVI B, 3EH - Move the data 3EH given in the
instruction to B register;

Direct Addressing
Address of the data is specified in the instruction
Data will be in memory
EX. LDA 1050H - Load the data available in memory
location 1050H in to accumulator

8085 ADDRESSING MODES(Contd..)

Register Addressing
Instruction specifies the name of the register in which the
data is available
EX. MOV A, B - Move the content of B register to A register

Register Indirect Addressing

The instruction specifies the name of the register in which
the address of the data is available
Data will be in memory and the address will be in the
register pair
EX. MOV A, M - The memory data addressed by H L pair is
moved to A register

8085 ADDRESSING MODES(Contd..)

Implied Addressing
The instruction itself specifies the data to be operated
EX. CMA - Complement the content of accumulator

8085 INSTRUCTION WORD SIZE

8085 instruction size is of 3 three types .They are
One byte/word instruction
Includes opcode and operand in same byte
Ex: MOV A,B (4FH)
Two byte/word instruction
1st byte specifies opcode
2nd byte specifies operand
Ex: MVI A,00 (3E,00)
Three byte/word instruction
1st byte specifies opcode
2nd byte specifies lower order address
3rd byte specifies higher order address
Ex: JMP 2085H (C3,85,20)

8085 TIMING DIAGRAM

Instruction cycle
Machine cycle
T state
Fetch operation and Execute operation
Fetch and execute cycle
4100
4102
4104
4105
4108

START: MVI A,95H

MVI B, 34H
ADD B
STA 4200H
HLT

 STEPS IN OPCODE FETCH

PC contents 4100
Place 4100 in address bus
00H in AD7-AD0
41H A15-A8
Initiate the RD control signal so that the memory will be
enabled
Place the opcode (3EH) in the data bus AD 7-AD0 and
transfer it to the instruction register
Decode the instruction in the IR and execute/take
appropriate actions

 Opcode fetch : (4 T-states / clock cycles)

T1 Address latch enable will be high
Lower order address from which instruction is to be read
will be present in AD7-AD0 during T1
Higher order address from which instruction is to be read
will be present in A15-A8 from T1 T3 and T4 it is
unspecified
Read signal will become active low during T2 and T3
So data will be present in AD7-AD0 during this time (T2
and T3)
T4 the instruction is decoded and executed/other actions
begin

TIMING DIAGRAM FOR OPCODE FETCH OF MVI A,95H

 MEMORY READ (3 T-states/clock cycles)

During T1 Address latch enable will be high
Lower order address from which data is to be read will
be present in AD7-AD0 during T1
Higher order address from which data is to be read will
be present in A15-A8 from T1 T3
Read signal will become active low during T2 and T3
So data will be present in AD7-AD0 during this time (T2
and T3)
There is no T4

TIMING DIAGRAM FOR MEMORY READ

 MEMORY WRITE (3 T-states/clock cycles)

During T1 Address latch enable will be high
Lower order address to which data is to be written will
be present in AD7-AD0 during T1
Higher order address to which data is to be written will
be present in A15-A8 from T1 T3
Write signal will become active low during T2 and T3
So data to be written will be present in AD7-AD0 during
this time (T2 and T3)
There is no T4

TIMING DIAGRAM FOR MEMORY WRITE

ADDRESS

HEXCODE

LABEL

INSTRUCTI
ON

4100

3E

START:

MVI A,95H

4101

95

4102

06

4103

34

4104

80

ADD B

4105

32

STA 4200H

4106

00

4107

42

4108

76

MVI B, 34H

HLT

DATA FLOW FOR MVI A,95H (1)

NOTE:
After fetching instruction from
4100H the contents of PC is
incremented to 4101H

DATA FLOW OF MVI A,95H (2)

NOTE:
After fetching instruction from
4101H the contents of PC is
incremented to 4102H

TIMING DIAGRAM OF MVI A,95H

TIME TO EXECUTE AN INSTRUCTION

CALCULATIONS
Clock of 8085 = 3 MHz
Time period (T)= 1/3MHz = 0.333 micro sec
No. of T- states required for MVI instruction is 4+3 = 7
Time to execute MVI instruction = 7(T state) x Time
period
= 7 x 0.333 s
= 2.331 s

DATA FLOW MVI B,34H (1)

DATA FLOW MVI B,34H (2)

NOTE:
After fetching instruction from
4103H the contents of PC is
incremented to 4104H

TIMING DIAGRAM MVI B,34H

DATA FLOW ADD B

NOTE:
After fetching instruction from
4104H the contents of PC is
incremented to 4105H

TIMING DIAGRAM OF ADD B

MACHINE CYCLE AND T-STATES OF STA

INSTRUCTION

DATA FLOW OF STA 4200H (ONLY OPCODE FETCH &MEMORY

READ)

DATA FLOW FOR MEMORY WRITEIN STA 4200H

Address bus
A15 A8 =42H
A7 A0 = 00H

MICROPROCESS
OR
Data bus
C9H

Write control signal

TIMING DIAGRAM FOR STA 4200H