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ARM7,ARM9,ARM11 Processors
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ARM history
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Why ARM?
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ARM processors
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Naming ARM
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ARMxyzTDMIEJFS
x: series - 7/9/11/cortex
y: MMU
z: cache
T: Thumb 16 bit instruction set
D: On chip Debug support
M: Enhanced Multiplier
I: Embedded ICE (built-in debugger hardware-)
E: Enhanced instruction
J: Jazelle (JVM): - 8 bit mode
F: Floating-point
S: Synthesizable version (source code version for EDA tools)
7/50
v4
Halfword and
signed halfword /
byte support
System mode
Thumb
instruction set
(v4T)
v5
Improved
interworking
Saturated arithmetic
DSP - MAC
instructions
Extensions:
Jazelle (5TEJ)
v6
SIMD Instructions
Multi-processing
v6 Memory architecture
Unaligned data support
Extensions:
Thumb-2 (6T2)
TrustZone (6Z)
Multicore (6K)
Thumb only (6-M)
v7
Thumb-2
Architecture Profiles
7-A
Applications
7-R - Real-time
7-M - Microcontroller
ARM7 - Features
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ARM7 - Applications
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ARM9 - Features
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ARM9 - Applications
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Product Type
Application
Consumer
Networking
Automotive
Embedded
Storage
ARM11 - Features
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ARM11 - Features
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ARM11 - Applications
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What is RISC?
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What is RISC?...
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1. Instructions
Reduced number of instruction classes to provide simple
operations that can each execute in a single cycle.
Each instruction is a fixed length to allow the pipeline to
fetch future instructions before decoding the current
instruction. (Unlike CISC)
2. Pipelines
The processing of instructions is broken down into smaller
units that can be executed in parallel by pipelines.
Ideally the pipeline advances by one step on each cycle for
maximum
throughput. Instructions can be decoded in
one pipeline stage.
3. Registers
RISC machines have a large general-purpose register set.
Any register can contain either data or an address.
Registers act as the fast local memory store for all data
processing
operations.
4. Load-Store Architecture
The processor operates on data held in registers.
Separate load and store instructions : transfer data between
the register bank and external memory.
Memory accesses are costly, so separating memory accesses
from data processing provides an advantage that use of data
items held in the register bank multiple times without needing
multiple memory accesses.
(CISC design : The data processing operations can act on
memory directly)
ARM Fundamentals
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TDMI
(Thumb instruction,
Debugger,
Multiplier, ICE)
power
1.
4.
6. Source operands are read from the register file using the
internal buses A and B, respectively.
7. The ALU (arithmetic logic unit) or MAC (multiplyaccumulate unit) takes the register values Rn and Rm
from the A and B buses and computes a result.
8. Data processing instructions write the result in Rd directly
to the register file.
9. Load and store instructions use the ALU to generate an
address to be held in the address register and broadcast on
the Address bus.
Programmers Model
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Registers
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Registers
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Registers
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Unbanked Registers
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Banked Registers
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Banked Registers
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Banked Registers
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Banked Registers
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Banked Registers
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T bit
The T bit reflects the operating state:
when the T bit is set, the processor is executing in
Thumb state
when the T bit is clear, the processor executing
in ARM state.
Interrupt Masks
Interrupt masks are used to stop specific interrupt requests
from interrupting the processor
The I and F bits are the interrupt disable bits:
when the I bit is set, IRQ interrupts are disabled
when the F bit is set, FIQ interrupts are disabled
Condition Flags
Condition flags are updated by comparisons and the result
of ALU operations that specify the S instruction suffix.
Processor Modes
Determines
1. which registers are active and
2. the access rights to the cpsr register itself
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Processor modes
1.Privileged
2.non-privileged
Privileged mode : Allows full read-write access to the cpsr
Non-privileged mode: allows only read operation access to the
control field in the cpsr but still allows read-write access to the
condition flags.
Pipeline
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Fetch :
Operating modes
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Operating modes
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Switching state
The operating state of the ARM7TDMI core can be
switched between ARM state and Thumb state using
the BX instruction.
All exception handling is entered in ARM state. If
an exception occurs in Thumb state, the processor
reverts to ARM state.
The transition back to Thumb state occurs automatically
on return.
An exception handler can change to Thumb state but
it must return to ARM state to allow the exception handler
to terminate correctly
Memory formats
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Memory formats
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Little-endian
Memory formats
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Big-Endian
Data types
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Exceptions
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Exceptions
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Entering an exception
1. Preserves the address of the next instruction in the
appropriate LR.
When the exception entry is from ARM state, the
ARM7TDMI processor copies the address of the next
instruction into the LR, current PC+4 or PC+8 depending
on the exception.
When the exception entry is from Thumb state, the
ARM7TDMI processor writes the value of the PC into
the LR, offset by a value, current PC+4 or PC+8
depending on the exception, that causes the program to
resume from the correct place on return.
Exceptions
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Entering an exception
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on
the exception.
4. Forces the PC to fetch the next instruction from the
relevant exception vector.
Exceptions
Leaving an exception
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Exceptions
Fast Interrupt Request
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Exceptions
Interrupt Request
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Exceptions
Abort
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Exceptions
Prefetch Abort
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Exceptions
Data Abort
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Exceptions
Data Abort
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Exceptions
Software interrupt instruction
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Exceptions
Undefined instruction
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Priorities of Exceptions
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Exceptions
Exception entry and exit summary
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Exceptions
Exception vectors
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Exceptions
Exception vectors
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Exceptions
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Interrupt latencies
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Interrupt latencies
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Interrupt latencies
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Reset
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Reset
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