SOC Design Flow

General Guidelines for Design Reuse

Synchronous design
Memory & Mixed signal design
Onchip buses
Clock distributions
Clear/set/reset/signals
Deliverable Models

Synchronous design
Data changes based on clock edges only, hence
instructions and data are easily manageable .
Use of registers in random logic as well as registration at
the inputs and outputs of every core.
Latch-based designs on the other hand are not easy to
manage because the data capture is not based on a clock
edge; instead, it requires a longer period of an active
signal.
Generally asynchronous loops and internal pulse generator
circuits should be avoided in the core design

 Multicycle paths and direct

combinational paths from block
inputs to outputs should be
avoided. If there are any
asynchronous clear and set
signals, then their deactivation
should be resynchronized.
The memory boundaries at
which read, write, and enable
signals are applied should be
synchronous and register-based

Memory & Mixed signal design

The memory design itself is technology dependent.
In large memories, the parasitics at the boundary cell are substantially
different than the parasitics of a cell in the middle of an array.
It is extremely useful to include rows and columns of dummy cells at
the periphery of large memories
Made as a part of the built-in self-repair (BISR) mechanism
In todays SOCs more than 60% of the chip is memories; mixed-signal
circuits make up hardly 5% of the chip area.
Most commonly used analog/mixed-signal circuits used in SoC are
PLLs, digital-to-analog converters (DACs), analog-to-digital
converters (ADCs),and temperature sensors.

Clock distributions
Any mismatch in clocking rules can impact the performance of an
entire SoC design.
Includes clock domain analysis, style of clock tree, clock buffering,
clock skew analysis, and external timing parameters such as setup/hold
times, output pin timing waveforms, and so on.
SoCs consist of multiple clock domains; it is always better to use the
smallest number of clock domains.
If two asynchronous clock domains interact, the interaction should be
limited to a single, small submodule in the design hierarchy & the
interface between the clock domains should avoid metastability

 A simple resynchronization method consists of clock

buffering and dual stage flip-flops or FIFOs at the clock
boundary
cores contain local PLLs, a low-frequency chip-level
synchronization clock should be distributed with on-chip
buses.
method to minimize clock skew is to edge-synchronize
master and derived clocks

Deliverable Models

Soft core Deliverables

Synthesizable Verilog/VHDL;
Example synthesis script;
RTL compiled module;
Structural compiled module;
Design, timing, and synthesis shells;
Functional simulation testbench;
Installation script;
Bus functional models and monitors used in testbenches;
Testbenches with sample verification tests;
Cycle-based simulation or emulation models;
Bus functional models;
Application note that describes signal slew rate at the inputs, clock
skew tolerance, output-loading range, and test methodology.

Hardcore Deliverables
Installation scripts;
ISA or behavioral model of the core;
Bus functional and fully functional models for the core;
Cycle-based emulation model (on request);
Floor planning, timing, and synthesis models;
Functional simulation testbench;
Bus functional models and monitors used in testbenches;
Testbenches with verification tests;
Manufacturing tests;
GDSII with technology file (Dracula deck);
Installation script;
Application note that describes timing at I/Os, signal slew rate,
clock distribution and skew tolerance, power, timing data sheet,
area, floor plan, porosity and footprint, and technology specifications.

Soft/Firm Core Design flow

Hard Core Design flow

Sign-Off Checklist

Completely synchronous design;

No latches in random logic;
No multicycle paths;
No direct combinational paths from
inputs to outputs;
Resynchronization at clock boundary;
Resynchronization of all asynchronous
set/reset/clear signals;
Synchronized write/read at memory
boundary;
Memory design and placement rule
checks;
Analog/mixed-signal circuits design
and placement rule checks;
Guard bands for memory and
analog/mixed-signal circuits;

Synchronization and protocol

verifications for on-chip buses;
Load balancing in clock tree;
Isolated clock domains;
Buffered clocks at the block boundary;
Clock skew within specified margin;
Registered block inputs/outputs;
No combinational feedback loops;
No internal tri-states;
No reconvergent logic;
Static timing analysis done;
Electromigration rules check;

 No DRC violations;
LVS and DRC checks for
custom circuits;
RTL and structural simulation
match;
RTL code coverage;
Gate-level simulation done;
Fault grading and simulation
done;
Fault coverage;

SDF (standard delay format)

back-annotated timing;
Functional simulation done;
DFT rules (such as scan rules)
check is done;
Timing, synthesis, test, design
shell files generated.