Digital Testing:

Test Pattern Generation

01/04/17

Based on text by S. Mourad

"Priciples of Electronic Systems" and
M. L. Bushnell and V. D. Agrawal,
Essentials of Electronic Testing for
Digital, Memory and Mixed-Signal
VLSI Circuits

Outline
Types of Tests
Deterministic Tests
Notations and Basic Operations
Design Verification
Critical Path
D-Algorithm
Reconvergent Fanout
PODEM
Other Algorithms
01/04/17

Copyright2001, Samiha Mourad

Deterministic Tests
NP-complete problem
Algebraic: Boolean Difference
General Fault Objective
Critical Path
Pseudo Random

Algorithmic
D-Algorithm Roth 1967 IBM
PODEM Goel 1981 IBM
FAN Fujiwara 1983 Kyoto U.
Socrates Schultz 1988 Germany
0/1 propagation Rajski 1990

01/04/17

Copyright2001, Samiha Mourad

The Basic Operations

Sensitization or Propagation
U=0

W sa1 fault

H=1

Justification
W/1
A=0

G1

B=0

G4

G3

Justification

E=1

Implication
C
G2

01/04/17

G5

Copyright2001, Samiha Mourad

Critical path tracing

A signal is critical if its change causes the
gate output change
if only one input has controlling
value => such input is critical
if all inputs have value c =>
all inputs are critical

Critical Path
1

1 0

1 0

000

011

100

111

Critical signals

(a)
U

U=0

G3

G1
B=0

G=1

G=0

W=1

A=0

G3
Z=1

G2

F=1

X=1

G5
H=1

W=1

A
G1
B=1

G4

Z=1
G2

X=0

G5
H=0

Y=1

F=0

G4

(b)
01/04/17

Copyright2001, Samiha Mourad

Critical path tracing

C
AND 0
OR
1
NAND 0
NOR 1

critical signals
Out
In
Out
0
0
1
1
1
0
1
0
0
0
1
1
single

In
111
000
111
000
all

start with the

output and
propagate path
towards input

Critical path tracing

Example: Start with critical 0c at the output and
propagate the critical signals backwards
h
f

d
a
b

c
e

j
g

Critical path tracing

Example :
a b c d e f g h i j k l
0C
1C 1C 1C 1C
0C
1
0C 1 0 C 0C 1

f
d
a
b
e

i
c

j
g

Make it critical by setting c to 1

Faults detected by the input (abde) = 0000

=> a1, b1, d1, e1, h0, i0, j0, k0, l0

Critical path tracing

Example: Find critical paths for q = 0c
a
b

c
d
e
f

g
h

Critical path tracing

a
b
c
d
e
f

Example :

a b c d e f g h i

o
k
l

g
h

k l m n o p q
0C
0C 0C 0C
1C 0C 1 1C 1C

1C 1C 0 0 0 C 0C 0 1C

Fault Oriented Algorithms

Fault Oriented Algorithms

Fault Oriented Algorithms

Read
netlist

A Generic Test
Algorithm

Generate fault list

Select one fault and

generate a pattern

Fault simulation

Remove all faults that are

detected by the pattern

Fault list empty

or desired FC
obtained?

01/04/17

Copyright2001, Samiha Mourad

Display
Results

14

Function of NAND Gate

Input a

1
0/1
D

Input b

D
1/0

D-Algorithm
Use D-algebra
Activate fault
Place a D or D at fault site
Do justification, forward implication and consistency check for
all signals

Repeatedly propagate D-chain toward POs through a

gate
Do justification, forward implication and consistency check for
all signals

Backtrack if
A conflict occurs, or
D-frontier becomes a null set

Stop when
D or D at a PO, i.e., test found, or
If search exhausted without a test, then no test possible

Definitions
Justification: Changing inputs of a gate if the
present input values do not justify the output
value.
Forward implication: Determination of the gate
output value, denoted as X, according to the input
values.
Consistency check: Verifying that the gate output
is justifiable from the values of inputs, which may
have changed since the output was determined.
D-frontier: Set of gates whose inputs have a D or
D, and the output is X.

Line justification in a fanout-free circuit

Justify (l, val)
begin
set l to val
if l is a PI then return
/* l is a gate (output) */
c = controlling value of l
i = inversion of l
input_val = val i
if (input_val = c)
then for every input j of l
Justify (j, input_val) --recursive call
else
begin
select one input (j) of l
Justify (j, input_val)
end
end

1
1

0
l

x
0
x

1
l

Error propagation in a fanout-free circuit

Propagate (l, err)
/* err is D or D */
begin
set l to err
if l is PO then return
k = the fanout of l
c = controlling value of k
i = inversion of k
for every input j of k other than l
Justify (j, c)
Propagate (k, err i)
end

l=

err
1

err
k

Definition: Singular Cover

A singular cover defines the least restrictive inputs for a
deterministic output value.
Used for:
Line justification: determine gate inputs for specified output.
Forward implication: determine gate output.

a
b

X
X

Examples:

XX0 110 = 110

0XX 0X1 = 0X1

Definition: D-Cubes
D-cubes are singular
covers with five-valued
signals
Used for D-drive
(propagation of D
through gates) and
forward implication.

a
b
Examples:

X
D

XDX 1DD = 1DD

0DX 0D1 = 0D1
DDX DD1 = DD1

Operations
0 1
1 0
1 1

111

F=x

W=1
X=D
{W,X,F} ={ 1,D,x}

X=D

A= 0
B=0

D'
(a) PDCF
W=1
X=D

F=D
{W,X,F} ={ 1,D,D}

(b) Propagation D-cube

W=1
E=x

F=1

W=x
E=x

F=1

(c) Justification

01/04/17

Copyright2001, Samiha Mourad

22

Propagation D-cubes
set selected inputs to D (D)
set remaining inputs to c
the output is D i (D i)
Example: For OR gate with (c=1, i=0)
and input D set the remaining inputs to 0
and the output is D

Primitive D-cubes of fault

for output equal to D (D) set :
all inputs to c (c) if i = c
one input to c (c) if i = c (other dont care)
Example: for AND gate (c=0, i=0) and output
equal to D (1/0) use all inputs equal
to 1

D-Intersection

0
1

Undefined
State
(conflict)

Set Operations
AND

D'

OR

D'

A'

D'

D'

D'

D'

D'

D'

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Copyright2001, Samiha Mourad

27

Testing for single stuck faults

Error propagation in a fanout-free circuit
Example : Propagate error in the following circuit
a
b

f sa0

c
d

h
j
i

Testing for single stuck faults

Error propagation in a fanout-free circuit
Example : Propagate error in the following circuit
a 1
b 1
c 0
d x
0
e

f sa0
D
0
g

D
1

D
j

Testing for single stuck faults

Example :
Propagate 6 sa0 fault in the circuit
1
2

G1

G3
7
G5

3
4

6
G2

sa0

G4

Testing for single stuck faults

Example :
Propagate 6 sa0 fault in the circuit
1
2

X
0

G1

G3

7
1

3
4

G2

9
D

0
0

G5

sa0

G4

Testing for single stuck faults

Example :

1
2

G1

G3

7
G5

3
4

G2

G1
1 2 5
X1 0
1X 0
0 0 1
singular
cover

G2
3 4 6
X0 D
0XD
1 1 D
pdcf

G3
3 5 7
0 X1
X 01
1 1 0
singular
cover

sa0

G4

G4
G5
2 6 8
7 8 9
0 D D
1 D D
D 0 D
D 1 D
D D DD D D
propagation propagation
D-cube
D-cube

Testing for single stuck faults

5

1
2

G1

G3

Example :

G5
3
4

G2

D-drive
1, select pdcf for 6 sa0
2, propagate through G4
3, propagate through G5
Consistency
4, use singular cover of G3
5, use singular cover of G1

sa0

G4

1 2 3 4 5 6 7 8 9 branch
X0
0 X0
0 X0

D
D D
D 1 D D

Y
Y
Y

0 X 0 0 D 1 D D
1 0 X 0 0 D 1 D D

N
N

Resulting test for 6 sa0 : T = 10x0

An Example: XOR
a2
a1
a
b

c1

c2
b1

b2
Find tests for:

c sa0
c1 sa0
c2 sa0

XOR: Test for c sa0

a2
a
b

a1

c1

c2

b1

b2
Action

Operation

D-frontier

1.

Activate fault c=1 or

c=c1=c2=D

d, e

2.

Justify c=1

0X1, a=a1=a2=0

d, e

3.

Forward impl a2=0

0D1, d=1

4.

Forward imp d=1

1XX

5.

D-drive c2e

D1D, b2=b=b1=1, e=D

6.

Forward impl b1=1

011,

7.

D-drive ef

1DD, f=D

8.

Stop, test found

Test: (a,b) = (0, 1), f = 1

, no implication possible
consistency checked

PO

Test-Detect: XOR, Test (0,1)

Determine good circuit signal values.
For each fault
Place a D or D at the fault site
Perform forward implications
Fault is detected if any PO assumes a D or D value
D for c1 sa0
a2
a
b

0 a1
1

b1
b2

D for c2 sa0

0D1 (null D-frontier) c1 sa0 not detected

c1
c
1 c2

1 d
1
D

0
D

1DX 1DD = 1DD, D at PO

c2 sa0 is detected
D1D

XOR: Test for c1 sa0

a2
a
b

a1

c1

c
b1

c2
e

b2
Action

Operation

D-frontier

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

c1=1 or c=c2=1, c1=D

0X1, a=a1=a2=0
0D1, d=1
No choice available
X01, b=b1=b2=0, a=X, d=X
101, e=1
X1X,
no implication possible
1DD, a2=a=a1=1,d=D
101,
consistency checked
D1D, f=D
Test: (a,b) = (1, 0), f = 1

d
d
null
null
d
d
d
f
f
PO

Activate fault
Justify c=1
Forward impl a2=0
Back-up, redo step 3
Back-up, redo step 2
Forward impl b2=0
Forward impl e=1
D-drive c1d
Forward impl a1=1
Forward impl d=D
Stop, test found

An Example
The circuit will be used to illustrate the D-algorithm for
faults on three different nodes
an internal node X
a primary input Y
a primary output Z
U =0
G3
W=1

A=0
G1
B=0

G
G2

X/0

G5
F

H
G4

U=0
G3

A=0
G1

Node X sa0 Fault

1

Operation

Initialization

PDFC

D-drive

D-drive

D-drive

10

11

Justification

12

13

Justification

14

01/04/17

Gate

G1

W=1

B=0

G2
X/0

F
G4

D
0

1
x

G3
0

D
x

D'

D'

G5
0
H=0
0
H=0
0

G2

x
0

0
0

D
0

0
D

x
1

G5

Copyright2001, Samiha Mourad

D'

0
D

D'

39

Compact Table
1

Operation

Initialization

PDFC

G1

D frontier

G2

D frontier

G3

D frontier

G5

D'

Justification

H=0

D'

Justification

H=0

D'

01/04/17

Gate

Copyright2001, Samiha Mourad

40

U =0
G3
W=1

A=0

G2

G1

Input Y sa1 Fault

Operation

Initialization

PDCF

D frontier

Implication

D frontier

7
8

H
G4

G4

F=1

G5

Justification

F =1

D'

Justification

X=1

D'

01/04/17

Gate

G5

X/0

B=0

Copyright2001, Samiha Mourad

41

U =0
G3
W=1

A=0

G2

G1

Operation

H
G4

Output Z sa0 Fault

Gate

PDCF

G5

Justification

Justification

Justification

Justification

01/04/17

G5

X/0

B=0

Copyright2001, Samiha Mourad

42

Multiple-Valued Algebras
Symbol

D
D
0
1
X
G0
G1
F0
F1

Fault-free Faulty
Alternative
Representation circuit
Circuit
1/0
0/1
0/0
1/1
X/X
0/X
1/X
X/0
X/1

1
0
0
1
X
0
1
X
X

0
1
0
1
X
X
X
0
1

Roths
Algebra
Muths
Additions

Complexity of D-Algorithm
Signal values on all lines (PIs and internal lines) are
manipulated using 5-valued algebra.
Worst-case combinations of signals that may be tried is 5 #lines
For XOR circuit, 512 = 244,140,625.
Podem: A reduced-complexity ATPG algorithm
Recognizes that internal signals depend on PIs.
Only PIs are independent variables and should be
manipulated.
Because faults are internal, a PI can assume only 3
values (0, 1, X).
Worst-case combinations = 3#PI; for XOR circuit, 32 = 8.

Podem Algorithm
Podem: Path oriented decision making
Step 1: Define an objective (fault activation, D-drive, or line
justification)
Step 2: Backtrace from site of objective to PIs (use testability
measure guidance) to determine a value for a PI
Step 3: Simulate logic with new PI value
If objective not accomplished but is possible, then
continue backtrace to another PI (step 2)
If objective accomplished and test not found, then define
new objective (step 1)
If objective becomes impossible, try alternative backtrace
(step 2)
Use X-PATH-CHECK to test whether D-frontier still there a
path of Xs from a D-frontier to a PO must exist.

XOR Example Again

Compute SCOAP testability measures: (CC0,CC1)CO
6

(4,2)3

5
(1,1)6

(3,2)5

(5,5)0

7
(1,1)6

5
6
(4,2)3

Podem: Objective and Backtrace

2&3. Backtrace to a PI
and simulate

(1,1)6
0

7
7

(1,1)6

1. Objective 1: set fault site to 1

6
5
sa0
D

(3,2)5
1

(4,2)3
1
(5,5)0

5
6

X-path check fails

(4,2)3 Back up:
Erase effects of steps 2&3
Try alternative backtrace

Podem: Back up
4&5. Alt. backtrace to a PI 1. Objective 1: set fault site to 1
and simulate
6
(4,2)3
(1,1)6
0
(1,1)6

(3,2)5
1

5
sa0
D

(5,5)0

X-path
1

6
(4,2)3

X-path check: OK
Objective 1 achieved

Podem: D-Drive
4. Objective 2: D-drive, set line to 1

5. Backtrace to a PI
and simulate

6
1

(1,1)6
1
0

7
7

(1,1)6

(3,2)5
1

(4,2)3
D

5
sa0
D

(5,5)0
D

5
1
6
(4,2)3

D at PO
Test found

Another Podem Example

3. Logic simulation for A=0

2. Backtrace A=0

1. Objective 0

S-a-1
(9, 2)

4. Objective possible but not accomplished yet

Podem Example (Cont.)

6. Logic simulation for A=0, B=0

5. Backtrace B=0

1. Objective 0

0
0

0
S-a-1
0

7. Objective possible but not accomplished yet

(9, 2)

Podem Example (Cont.)

9. Logic simulation for E=0

8. Backtrace E=0

1. Objective 0

0
0
0

0
0

S-a-1
0

10. Objective possible but not accomplished yet

(9, 2)

Podem Example (Cont.)

12. Logic simulation for D=0
1. Objective 0

0
0
0

0
0

S-a-1
0

0
(9, 2)
11. Backtrace D=0

13. Objective accomplished

START

Assign a binary value to an

unassigned primary input

PODEM
Flowchart

Determine implications of all

primary inputs

yes

Test has been

generated

Is there a D or a D
on any primary ouput?

no
Test possible
with the additional
assigned primary
inputs?

maybe
no

No Pattern
Exists

no

Is there an
untried combination of
values on assigned
primary inputs?

yes
Set untried combination of
values on assigned primary
inputs

01/04/17

Copyright2001, Samiha Mourad

57

PODEM Example E sa1 Fault

1.
Assign x to all inputs
2.
Assigning 0 to the primary input, U, causes E = 1; hence, this choice
does not further our goal and it is discarded. Then U =1
3.
We proceed with W = 1. The implication of this value is not
furthering the objective nor is it blocking it.
4.
X = 1 is rejected and X=0 is selected.
5.
This Implies F=0, H=0 and we can propagate D on G, then D on the
primary output, Z.

G1 E=D

G3

G=D
0

G2

G5
F

H
G4

01/04/17

Z =D

0
1

Copyright2001, Samiha Mourad

U
W

1
58

PODEM Example G sa1 Fault

1.
Assign x to all inputs
2.
Assigning 0 to the primary input, W, causes G = 1; hence, this choice
is discarded. Then W =1 which causes F=0.
3.
We proceed with X = 1. The implication of this value is not
furthering the objective nor is it blocking it.
4.
Similarly V=1 is selected.
5.
E=1 is rejected, so E=0 which implies I=1 and we can propagate D on
the primary output, Z.

G1

F
G4

W
X

G2

W
X

G =D
V

0
V

E
01/04/17

G3

G5

Z =D

1
I
Copyright2001, Samiha Mourad

1
59

Other Algorithms
FAN
A variation of PODEM with better heuristic to
prune the search tree for backtracking

Socrates
A variation of FAN using testability analysis to
cut down on backtracking

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Copyright2001, Samiha Mourad

60

Comparing FAN to PODEM

Computing Time

Average Backtracks

%age of Faults Aborted

PODEM

FAN

PODEM

FAN

PODEM

FAN

1.3

4.9

1.2

0.32

0.37

3.6

42.3

15.2

2.26

3.13

5.6

61.9

0.6

2.42

4.00

1.9

5.0

0.2

0.99

1.10

4.8

53.0

23.2

0.82

1.02

Circuit

01/04/17

Copyright2001, Samiha Mourad

61

Multi fault detection with

01 sequence (Dr. Janusz Rajski)
1, Drive backward from output 01 to
establish 2 test vectors
2, Propagate forward (with fault effects)
3, Analyze the results (backward)

Rajskis method
Example : ABCE = (00, 11, 01, 11)

C=01,00,11

A=00,11

B=11,00
G5=01,11,00

G2=01,00,11

G1=01,00,11
E=11,00

G4=10,11,00
G8=00,11
B=00,11

G3=00,11

G6=00,10,11

If single fault

G7
01,11,0
0

Rajskis method
Example : ABCE = (00, 11, 00, 10)

C=00

A=00

B=11
G2=00

G5=00
G7=01

G1=00
E=10,11

G4=11,00

G8=01,00,11
G3=01,00,11
B=00,11

G6=01,00

Rajskis method
Example : ABCE = (10, 00, 00, xx)
B=00,11
C=00

A=10

G5=00,10

G2=10

G7=01

G1=00
E=xx

G4=01
G3=11
B=11

G6=01

Rajskis method
Example :
multiple faults
coverage

A
B
C
E
G1
G2
G3
G4
G5
G6
G7
G8

sa1
x
3
x
2
x
x
x
3
x
x
x
x

sa0
3
x
x
x
x
x
2
2
x
2
x
2

Rajskis method

sa0

Multiple faults
Example :
a
b

00,11
00,11

01,00,11

00,11

11,00

00,11

000010
abcdef
001010
g

11,00

h
01,11,00

01,11,00

h1= 01,11,00
h2= 01,11,00
01,11,00

a
b
c
d
e
f
g
h
h1
h2
i
j
k
Z

sa1
x
x
x
x

x
x
x
x
x
x
x
x
x
x

x
x

01,11,00

k
Z
01,11,00

Rajskis method
Example :
a
b

10,00,11
00,11

100110
abcdef
000110
g

01,00,11

00,11

11,00

11,00

if single fault

11,00

00,11

01,00,11

h1= 11,00

sa0
2

a
b
c
d
e
f
g
h
h1
h2
i
j
k
Z

sa1
x
x
x
x

x
x
x
x
x
x
x
x
x

x
2
x
2
x
x

01,00,11

h2= 11,00

j
11,00

k
Z
01,00,11

Rajskis method
Example : ABCE = (00, 11, 01, 11)
single fault test critical signals are
underlined
C=01,00,11

A=00,11

B=11,00
G5=01,11,00

G2=01,00,11

G1=01,00,11
E=11,00

G4=10,11,00
G8=00,11
B=00,11

G3=00,11

G6=00,10,11

G7
01,11,0
0

Example :
Using
Rajskis
method

10,00,11
10,00,11

00,11

Example :
Using
Rajskis
00,11
method

01,00,11
00,11
00,11
01,00,11
11,00
00,11

11,00

11,00
00,11

00,11

11
00,11
11,00