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01/11/17
Sequential Machine
A digital computer is a sequential machine.
The CPU (microprocessor) executes instructions in a
sequence as specified by the program.
In general terms the instructions are executed in the
sequence they are written.
However a certain class of instruction can vary the
instruction execution sequence.
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Instruction Fetch
Processor places address
of where the instruction is
stored onto address bus
Processor asserts the read
control line
The memory device places
the data at the addressed
location onto the data bus
The processor reads the
instruction byte.
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Instruction Format
Instructions are stored in program
memory in binary coded form.
Since an instruction must represent a
complete and unambiguous statement of
the operation required of the processor
then 8-bits (the number of bits of a single
memory location) is often insufficient to
specify the complete instruction.
Depending on the particular instruction,
8085A instructions occupy one, two or
three successive memory locations.
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The Opcode
The first byte of an instruction is called the
Opcode
It describes :
The operation to be carried out e.g move data,
arithmetic operation, logical operation etc
Where the source data is located in the computer
The destination for the result of the operation
How many bytes constitute the complete instruction
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Example of Opcode
Consider the instruction: STA addr
Opcode in assembly language form STA
Opcode in machine language form (i.e. the bits that are actually stored in memory) 00110010 (32H)
The opcode specifies :
Data is to be moved
The source of the data is the CPU register A
The destination for the data is external memory
The complete instruction is three bytes long
Bytes 2 & 3 of the instruction specify the address of the memory location
where the data is to be written.
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Example of Instruction
Execution
The following are the sequence of operations the processor is
required to perform to execute the instruction
STA addr
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Example of Instruction
Execution
The whole of the instruction has been fetched at this stage. The 8bit temporary registers W & X contain the 16-bit address of the
memory location at which the contents of CPU register A is to be
stored.
The execution phase of the instruction can now take place.
Place the contents of W & X onto the address bus ; specify memory address
Place the contents of register A onto data bus
; data to be written
Assert WR control signal
; write data to memory
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<destination> <source>)
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LXI
SP, data 16
17
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The Sign Flag (S) reflects the contents of bit-7 of the accumulator
The Zero Flag (Z) is set to 1 if the accumulator contains all zeros
The Carry Flag (CY) is set if the arithmetic operation caused a carry
overflow (from addition) or a borrow (from subtraction).
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; A contains 88 (H)
B contains 99 (H)
register A
10001000
136
decimal register B
10
011001
153
decimal _____________
_____
register A
100100001
289
decimal
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CLK out (o) Is a buffered version of the internal master clock of the
8085A. It is half the crystal frequency.
HOLD (i) HLDA (o) An external device can request use of the system
busses by driving the HOLD input to logic 1. The
8085A acknowledges the request by asserting the
HLDA output to logic 1. It only does after it has
relinquished control of the bus structure.
ALE (o) When this signal is logic 1 the processor specifies that
it has valid address information on the CPU pins AD07
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Address Latches
Peripheral devices ( memory and IO ) require stable address
data throughout a read or write operation.
The processor only provides A0 - A7 during the period ALE is in
the logic 1 state after which the multiplexed lines AD0 - AD7
assume the role of the data bus. ( D0 - D7 )
To provide external devices with stable address data throughout
a read or write operation it is necessary to latch the low byte of
the address using the ALE control signal.
By this mechanism it is possible for the 8085A computer system
to have a 16-bit address bus and an 8-bit data bus whilst only
using 16 processor connections ( AD0 - AD7 and A8 - A15 )
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