Pass-Transistor Logic Circuits (2)

An essential requirement in the design of pass-transistor logic is

ensuring that every circuit node has at all times a low-resistance path to
VDD or to ground.
If B is high, S1 closes and Y=A.
Y will be VDD if A is high or ground if
A is low.

If B is low, S1 opens and Y becomes

a high-impedance node.
If voltage of Y is initially zero, it will
remain so.
If voltage of Y is initially high at VDD,
then the inevitable leakage current will
discharge the C and can no longer be
considered a static circuit.

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 Pass-Transistor Logic Circuits (3)

The problem can be easily solved by establishing for node Y a low-

resistance path that is activated when B goes low.

Another switch, S2, controlled by B

is connected between Y and ground.
When B goes low, S2 closes and
establishes a low-resistance path
between Y and ground.

Figure 15.7 A basic design requirement of PTL circuits is that every node have, at all times, a low resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in
(b) through switch S2.

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 Operation with NMOS as Switches (3)

2 methods are proposed to solve the aforementioned signal-level loss

(VOH=VDD-Vt) problem.
Circuitbased technology.
If vO1 is high but not equal to VDD
vO2 is low
QR turns on
supplying a current to charge C to VDD.
This arrangement of QR is somewhat
involved since it creates the positive-
feedback loop around the CMOS inverter.
Fortunately, it is the weak PMOS.
Process technology. If the Vt can be reduced, the signal-level loss would
become less significant. Device with Vt=0 is known as natural device.

Figure 15.10 The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the
VOH level, produced by Q1, to VDD.
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