NAND AND FLASH ROMs

NAND ROM
The structure uses active-low wordlines. Transistors
are placed in series and the transistors on the non-
selected rows are ON.
If no transistor is associated with the selected
word, the bitline will pull down. If a transistor is
present, the bitline will remain high. The contents
are specified by using either a transistor or a metal
jumper in each bit position.
In this design, an extra implantation step can be
used to create a negative threshold voltage,
turning certain transistors permanently ON where
they are not needed.
Layout of the NAND ROM
 Disadvantage and
advantages
Its delay grows quadratically with the
number of series transistors discharging
the bitline.
NAND structures with more than 816
series transistors become extremely slow.
So ROMs are often broken into multiple
small banks with a limited number of series
transistors.
Due to its less density and cost, it is
preffered in flash memories.
 FLASH ROM: Applications

Flash memory cards are widely used in digital

cameras to store hundreds of high-resolution
images.
Flash is also useful for firmware or
configuration data because it can be rewritten
to upgrade a system in the field without
opening the case or removing parts.
Flash memory has become tremendously
popular because of its nonvolatile storage and
exceptionally low cost per bit.
 Flash Memory Operation
It uses the NAND architecture to minimize bit
cell size and cost. Its memories are divided
into blocks, which in turn are made of pages.
The memory is written one page at a time and
erased one block at a time.
Flash uses floating gate transistors as memory
cells. The charge on the floating gate
determines the threshold of the transistor and
indicates the state of the cell. A negative
threshold represents a logic 1 and a positive
threshold represents a logic 0.
 In NAND Flash, the floating gate transistors are connected
in series to form strings. Each string consists of 16 cells, a
string select transistor, and a ground select transistor all
connected in series and attached to the bitline.
The array contains one column for each bit in a page.
Each column contains one string per block. The number of
cells in the string determines the number of pages per
block. The block is erased by setting all of the control
gates to GND and raising the substrate to 20 V. The high
voltage across the gate oxide induces FN tunneling,
causing the electrons to flow from the floating gate to the
substrate. At the end of the erase step, all the floating
gate transistors have a negative Vt and thus represent 1.
 Tunneling is a slow process, so block erase takes on the order
of a millisecond. The wordlines for other blocks on the chip are
set to the same voltage as the substrate to inhibit erasing. An
on-chip charge pump is used to generate the high voltages. A
cell is programmed (written) to 0 by tunneling electrons onto
the floating gate. The programming cannot restore 1 values, so
the block must be erased before any cell is reprogrammed. An
entire page is programmed at once. To program a page, the
bitlines are driven with the data values: 0 V for a logic 0 and 8
V for a logic 1. The substrate is held at ground. The wordline is
set to 20 V for the page being programmed and 10 V for the
other pages in the block. The ground select line (gsl) is left OFF
but the string select line (ssl) for the block is turned ON,
passing the voltage on the bitline to the channels of all the
transistors being programmed.
 Thus, cells being programmed to 0 see 20 V on the control
gate and 0 V on the channel. This high voltage difference
induces FN tunneling that drives electrons onto the floating
gate, raising Vt to a positive voltage. The other cells see a
smaller voltage that is insufficient to cause tunneling. A
page is read in a similar fashion to a conventional NAND
ROM. The bitlines are precharged. ssl and gsl are both set to
3.3 V to activate the selected block. The active-low wordline
for the selected page is set to 0 V and the wordlines for all
the other pages in the block are set to 4.5 V, which is much
higher than Vt. Thus, all the transistors in the stack are ON
except possibly the one corresponding to the selected page.
If the cell being read has a negative Vt , it turns ON too and
the bitline discharges.
 If the cell being read has a positive Vt, it remains OFF and
the bitline does not switch. To achieve higher densities,
multilevel Flash cells store more than one bit on a
transistor by programming the threshold to one of several
levels. The threshold can be sensed by adjusting the
voltage on the selected wordline. The number of bits that
can be stored depends on how accurately the threshold
can be programmed and sensed. Two reliability metrics for
Flash memories are retention time and endurance. The
retention time is the duration for which a Flash cell will hold
its value. Under normal conditions, the charge on the
floating gate would take thousands or millions of years to
leak off. However, defects in the oxide may increase
leakage for some cells.
 Manufacturers typically specify a 10 year retention time.
Endurance is the number of times that a cell can be
erased and reprogrammed. The high voltages stress the
oxide and can eventually cause it to wear out. Endurance
of 100,000 erase-program cycles are typical, but some
multilevel Flash cells have endurance as low as 5000
cycles. Some foundries offer an embedded Flash option, in
which extra masks and process steps are used to create
the floating gate transistors. The embedded Flash is
commonly used for code storage in applications such as
microcontrollers. These applications typically use NOR
Flash instead of NAND because they need fast access to
individual words rather than slow access to entire pages.