JFET & MOSFET

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 FET

Field Effect Transistor (FET) is unipolar

transistor.
Its operation depends on only one type of
charge; either electron or hole
FET is voltage controlled device
FET has very high input impedance (around
100M)
Three terminals Drain, Gate and Source

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 FET
FET Classification

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Junction Field Effect
Transistor (JFET)

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 JFET
JFET

The n channel FET is formed by diffusing one pair

of p region in to a slab of n type material
Similar to two diodes the gate-source diode and
gate-drain diode
In n channel the electron flow is from source to
drain 5
 JFET
Basic operation of n channel JFET

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 JFET
VDD provides voltage across drain and source so
as to generate a current flow from drain to source
VGG provides the gate source voltage. Since
voltage across gate and source is reverse biased
no gate current will be generated
The depletion region generated by this gate
voltage at the sides of the channel will narrow the
width of the channel, which will increase the
resistance between drain and source and further
decrease the drain current

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 JFET
When VGS=0,

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 JFET
A voltage drop will be developed by VDD, when a
current flows through the n channel viewed as a
small resistor
The potential close drain gate junction is higher
than source gate junction
The reverse bias applied to PN junction will form a
depletion layer
When the voltage source VDD is increased, the
current ID also increases. The depletion layer also
becomes larger and drain source resistance
increases
If VDD is continuously increased, depletion layer9
 JFET
Any further increase in VDD will not increase ID any
more (I=V/R V increases, R increases, I is kept
constant)
Channel is said to be pinched off
This constant value of ID is referred as IDSS

(DS indicates current from drain to source

and second S means it is under the status
that source-gate are short circuit (Vgs=0)

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JFET

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 JFET
If VGS is increased (more negative for n-channel) depletion
will be immediately developed in the channel so that
current required to pinch off the channel is reduced.
This implies that the gate voltage controls the drain
current
If VGS is more positive for p-channel JFET, I D will be
decreased from IDSS
If VGS is continuously increased, I D will be decreased
correspondingly
At certain value of VGS, will be decreased to zero and will
be independent of the value of V DS
The gate source voltage at this point is called the pinch
off voltage (VP or VGS(cutoff))
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 JFET
Gate cut off voltage gate voltage at which the
drain current is zero.
Pinch off voltage drain voltage at which the
highest drain current curve changes form almost
vertical to almost horizontal
Active region Constant/horizontal drain current
region
Ohmic region / Saturation region vertical part of
the drain current
Cutoff region part of the curve when drain current
is zero
Breakdown voltage max. drain voltage the JFET
can withstand 13
 JFET
JFET Transconductance Curve This is the
curve of variation in drain current with respect to
gate-source voltage while the drain-source
voltage remains constant
VGS
I D I DSS (1 )2
VGS ( off )

IDSS stands for the drain source current with

shorted gate. This is the maximum drain current a 14
Metal Oxide Semiconductor
Field Effect Transistor
(MOSFET)

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 MOSFETs
MOSETs
Metal Oxide semiconductor FETs depends on the fact
that it is not actually necessary to form a
semiconductor junction on the channel of a FET to
achieve gate control of channel current
Also called IGFET (Insulated Gate FET)
Unlike JFET, the gate is electrically isolated from the
channel by a thin layer of silicon dioxide
Hence the gate current is extremely small irrespective
of whether the gate is positive or negative
Two types
Depletion mode MOSFET quite similar to JFET
Enhancement mode MOSFET
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 MOSFET
N channel depletion type MOSFET

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 MOSFET
The P region is called the substrate (or body)
Electrons flowing from source to drain must
pass through the narrow channel between the
gate and the p region
Depletion mode MOSFET with negative
bias & positive bias

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 MOSFET
Negative bias (same as JFET)
As with JFET, more negative the gate voltage,
the smaller the drain current
When the gate voltage is negative enough, the
drain current is cut off
Positive bias (different from JFET)
The positive gate voltage increases the number
of free electrons
The more positive the gate voltage, the greater
the conduction from source to drain

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 MOSFET
Drain curve & Transconductance curve

Upper curves have a positive VGS

Lower curves have a negative VGS

The bottom curve is for VGS=VGS(off)

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 MOSFET
When VGS is between VGS(off) and zero, we get
depletion mode operation
And when VGS greater than zero, we get
enhancement mode operation

IDSS is the drain current with

shorted gate

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 MOSFET
Enhancement mode MOSFET (N channel)

The substrate extends all the way to the silicon

dioxide
There is no longer an n-channel between drain and
source

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 MOSFET
When the gate voltage is zero, the V DD supply
tries to force free electrons from source to
drain, but the p substrate has only a few
thermally produced free electrons
Aside from these minority carriers and some
surface leakage, the current between source
and drain is zero
For this reason the enhancement mode
MOSFET is normally off when the gate volatge
is zero

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 MOSFET
When the gate voltage is positive, it attracts free
electrons into the P region
The free electrons recombines with the holes next
to the silicon dioxide
When the gate voltage is positive enough all the
holes touching the silicon dioxide are filled and free
electrons begin to flow from the source to the drain
The effect is same as creating a thin layer of n-
type material next to the silicon dioxide
This conducting layer is called the n-type
inversion layer

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 MOSFET
The minimum VGS that creates the inversion
layer is called the threshold voltage VGS(th)
Depending upon the device the VGS(th) can vary
from less than 1 to more than 5V

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 MOSFET
Reading Data Sheet
VDS
VGS
ID
PD
TJ
RJC
RDSON
VGS(th)

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