MIPS

Instruction Set Design - Goals
Maximize Performance
Minimize cost
Reduce Design time (time-to-market)
minimize memory space (embedded systems)
minimize power consumption (mobile systems)
2004 Morgan Kaufmann Publishers 1

RISC - Reduced Instruction Set Computer
RISC philosophy
fixed instruction lengths
load-store instruction sets
limited number of addressing modes
limited number of operations
MIPS, Sun SPARC, IBM PowerPC
Instruction sets are measured by how well compilers use them as

opposed to how well assembly language programmers use them
CISC (C for complex), e.g., Intel x86

Instruction Set Architecture
(MIPS: Microprocessors without Interlocked

Pipeline Stages)
Four design principles guide

Simplicity favors regularity
Smaller is faster
Make the common case fast
Good design demands good
compromises
Instructions:
Language of the Machine

Well be working with the MIPS instruction set architecture
similar to other architectures developed since the 1980's
Almost 100 million MIPS processors manufactured in 2002
used by NEC, Nintendo, Cisco, Silicon Graphics, Sony,
1400
Other
1300
SPARC
1200 Hitachi SH
1100 PowerPC
Motorola 68K
1000
MIPS
900 IA-32
800 ARM
700
600
500
400
300
200
100
0
1998 1999 2000 2001 2002

Instruction set: The vocabulary of
commands understood by a given
architecture.
Stored-Program Concept : The idea that

instructions and data of many types can be
stored in memory as numbers, leading to
the stored program computer.

2.2 Operations of the Computer Hardware

MIPS arithmetic
All instructions have 3 operands

Operand order is fixed (destination first)
Example:
C code: a = b + c
MIPS code: add a, b, c
(well talk about registers in a bit)
The natural number of operands for an operation like addition is

threerequiring every instruction to have exactly three operands, no
more and no less, conforms to the philosophy of keeping the
hardware simple

Smaller is faster
compromises

FIGURE 2.1 MIPS architecture revealed in section 2.2.
MIPS assembly language

Category Instruction Example Meaning Comments
Arithmetic add add a, b, c a=b+c Always three operands
subtract sub a, b, c a=b-c Always three operands

f = (g+h) - (i+j);
add t0, g, h
add t1, i, j
sub f, t0, t1

MIPS arithmetic
Design Principle: simplicity favors regularity.

Of course this complicates some things...
C code: a = b + c + d;
MIPS code: add a, b, c

add a, a, d
Operands must be registers, only 32 registers provided

Each register contains 32 bits
Design Principle: Smaller is faster. Why?

f = (g+h) - (i+j);
$s0, $s1, $s2, $s3, $s4
add t0, $s1, $s2

add t1, $s3, $s4
sub $s0, t0, t1
Assuming variable b is stored in register $s1, c is stored in $s2, and
d is stored in $s3 and the result is to be left in $s0, what is the
assembler equivalent to the C statement
h = (b - c) + d
sub $t0, $s1, $s2

add $s0, $t0, $s3

2.3 Operands of the Computer Hardware

Data transfer instruction: a command
that moves data between memory and
registers.
Address: A value used to delineate the
location of a specific data element
within a memory arry.

Registers vs. Memory
Arithmetic instructions operands must be registers,

only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables
Control Input
Memory
Datapath Output
Processor I/O

Smaller is faster
compromises

Memory Organization
Viewed as a large, single-dimension array, with an address.

A memory address is an index into the array
"Byte addressing" means that the index points to a byte of memory.
0 8 bits of data
1 8 bits of data
2 8 bits of data
3 8 bits of data
4 8 bits of data
5 8 bits of data
6 8 bits of data
...

Memory Organization
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
0 32 bits of data
4 32 bits of data
Registers hold 32 bits of data
8 32 bits of data
12 32 bits of data
...
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
Words are aligned
i.e., what are the least 2 significant bits of a word address?

FIGURE 2.2 Memory addresses and contents of
memory at those locations.

FIGURE 2.3 Actual MIPS memory addresses and
contents of memory for those words.

Compiling with Loads and Stores
Assuming variable b is stored in $s2 and that the base address of

array A is in $s3, what is the MIPS assembly code for the C statement
A[8] = A[2] - b
... ...
A[3] $s3+12
A[2] $s3+8
A[1] $s3+4
lw $t0, 8($s3)
A[0] $s3
sub $t0, $t0, $s2
sw $t0, 32($s3)

g = h + A[8]
lw $t0, 8($s3)
add $s1, $s2, $t0

Instructions
Load and store instructions

Example:
C code: A[12] = h + A[8];
MIPS code: lw $t0, 32($s3)

add $t0, $s2, $t0
sw $t0, 48($s3)
Can refer to registers by name (e.g., $s2, $t2) instead of number

Store word has destination last
Remember arithmetic operands are registers, not memory!
Cant write: add 48($s3), $s2, 32($s3)

Dealing with Constants
Small constants are used quite frequently (50% of operands in
many common programs)
e.g., A = A + 5;
B = B + 1;
C = C - 18;
Solutions? Why not?
Put typical constants in memory and load them
How do we make this work?

How do we Make the common case fast !

Constant (or Immediate) Operands
Include constants inside arithmetic instructions
Much faster than if they have to be loaded from memory
(they come in from memory with the instruction itself)
MIPS immediate instructions
addi $s3, $s3, 4 #$s3 = $s3 + 4
There is no subi instruction, can you guess why not?

MIPS Instructions, so far
Category Instr Example Meaning
Arithmetic add add $s1, $s2, $s3 $s1 = $s2 + $s3
subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3
add immediate addi $s1, $s2, 4 $s1 = $s2 + 4
Data load word lw $s1, 32($s2) $s1 = Memory($s2+32)

transfer
store word sw $s1, 32($s2) Memory($s2+32) = $s1

Smaller is faster
compromises

FIGURE 2.4 MIPS architecture revealed through
section 2.3.
MIPS operands
Name Example Comments
$s0, $s1, , $s7 Fast locations for data. In MIPS, data must be in registers to perform arithmetic.
32 registers
$t 0, $t 1, , $t 7 Registers $s0 - $s7 map to 16-23 and $t0 - $t7 map to 8-15.
Memory[0],
230memory
Memory[4], ,
Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses,
words so sequential word addresses differ by 4.
Memory[4294967292]

add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers
Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers
add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory [$s2 + 100] Data from memory to register
Data transfer
store word sw $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Data from register to memory

2.4 Representing Instructions in the
Computer

Binary digit Also called binary bit. One of
the two numbers in base 2, 0 or 1, that are
the components of information.
Machine language: Binary representation
used for communication within a computer
system.
Instruction format: A form of representation
of an instruction composed of fields of
binary numbers.

Machine Language
Instructions, like registers and words of data, are also 32 bits long
Example: add $t1, $s1, $s2
registers have numbers, $t1=9, $s1=17, $s2=18
Instruction Format:
000000 10001 10010 01001 00000 100000
op rs rt rd shamt funct
Can you guess what the field names stand for?

op: Opcode
rs: the first register source operand.
rt: the second register source operand.
rd: the register destination address.
shamt: Shift amount. (for shift instructions)
funct: Function (function code) ( selects the
specific variant of the operation specified in the
opcode field)

Machine Language
Consider the load-word and store-word instructions,

What would the regularity principle have us do?
New principle: Good design demands a compromise
Introduce a new type of instruction format
I-type for data transfer instructions
other format was R-type for register
Example: lw $t0, 32($s2)
35 18 8 32
op rs rt 16 bit number
Where's the compromise?

Smaller is faster
compromises

section 2.4
MIPS machine language

Name Format Example Comments
add R 0 18 19 17 0 32 add $s1, $s2, $s3
sub R 0 18 19 17 0 34 sub $s1, $s2, $s3
addi I 8 18 17 100 addi $s1, $s2, 100
lw I 35 18 17 100 lw $s1, 100($s2)
sw I 43 18 17 100 sw $s1, 100 ($s2)
Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits ALL MIPS instructions 32 bits
R-format R op rs rt rd shamt funct Arithmetic instruction format
I-format I op rs rt address Data transfer format

2.5 Logical Operations

FIGURE 2.9 C and JAVA logical operators and their
corresponding MIPS instructions.
Logical operations C operators JAVA operators MIPS instructions

Shift left << << sll
Shift right >> >>> srl
Bit-by-bit AND & & and, andi
Bit-by-bit OR | | or, ori
Bit-by-bit NOT ~ ~ nor

FIGURE 2.10 MIPS architecture revealed thus far.
MIPS operands
32 registers
$t 0, $t 1, , $t 7 Registers $s0 - $s7 map to 16-23 and $t0 - $t7 map to 8-15.
Memory[0], Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses,
230memory Memory[4], , so sequential word addresses differ by 4. Memory holds data structures arrays,
words
Memory[4294967292] and spilled registers.

add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; Overflow detected
Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; Overflow detected
add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 +constant; overflow detected
and add $s1, $s2, $s3 $s1 = $s2 & $s3 Three reg. operands; bit-by-bit AND
or or $s1, $s2, $s3 $s1 = $s2 | $s3 Three reg. operands; bit-by-bit OR
nor nor $s1, $s2, $s3 $s1 = ~($s2 | $s3) Three reg. operands; bit-by-bit NOR
and immediate andi $s1, $s2, 100 $s1 = $s2 & 100 Bit-by-bit AND reg with constant
Logical
or immediate ori $s1, $s2, 100 $s1 = $s2 | 100 Bit-by-bit OR reg with constant
shift left logical sll $s1, $s2, 10 $s1 = $s2 << 10 Shift left by constant
shift right srl $$s1, $s2, 10 $s1 = $s2 >> 10 Shift right by constant
logical
Data load word lw $s1, 100($s2) $s1 = Memory [$s2 + 100] Word from memory to register
transfer store word sw $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Word from register to memory

2.6 Instructions for Making Decisions

Conditional branch: An Instruction that
requires the comparison of two values and
that allows for a subsequent transfer of
control to a new address in the program
based on the outcome of the comparison.
Basic block: A sequence of instructions
without branches and without branch
targets or branch labels.
Jump address table also called jump table.
A table of addresses of alternative
instruction sequences.

Compiling if-then-else into Conditional Branches
if (i==j) f=g+h; else f=g-h;
bne $s3, $s4, Else

add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:

FIGURE 2.11 Illustration of the options in the IF
statement above.

Control
Decision making instructions

alter the control flow,
i.e., change the "next" instruction to be executed
MIPS conditional branch instructions:
bne $t0, $t1, Label

beq $t0, $t1, Label
Example: if (i==j) h = i + j;
bne $s0, $s1, Label

add $s3, $s0, $s1
Label: ....

Assembling Branches
Instructions:
bne $s0, $s1, Lbl #go to Lbl if $s0$s1
beq $s0, $s1, Lbl #go to Lbl if $s0=$s1
Machine Formats:
op rs rt 16 bit number I format
5 16 17 ????
How is the branch destination address specified?
4 16 17 ????

Specifying Branch Destinations
Could specify the memory address - but that
would require a 32 bit field
Could use a base register and add to it the
16-bit offset
which register?
Instruction Address Register
(PC = program counter) - its use
PC bne $s0,$s1,Lbl1 is automatically implied by branch
PC gets updated (PC+4) during
add $s3,$s0,$s1
the Fetch cycle so that it holds the
Lbl1: ... address of the next instruction
limits the branch distance to -215 to
+215-1 instrs from the (instruction after
the) branch
but most branches are local
anyway
Disassembling Branch Destinations
The contents of the updated PC (PC+4) is added to the 16 bit branch
offset which is converted into a 32 bit value by
concatenating two low-order zeros to make it a word address and
then sign-extending those 18 bits
The result is written into the PC if the branch condition is true - before
the next Fetch cycle
from the low order 16 bits of the branch instruction Fetch

16 PC = PC+4
sign-extend offset
Exec Decode
00
branch dst
32 32 Add
address
PC 32 Add 32
32
32 4 32 ?
Offset Tradeoffs
Why not just store the word offset in the low order 16 bits? Then the
two low order zeros wouldnt have to be concatenated, it would be
less confusing,
That would limit the branch distance to -213 to +213-1 instrs from the
(instruction after the) branch
And concatenating the two zero bits costs us very little in additional
hardware and has no impact on the clock cycle time

Assembling Branches Example
Assembly code
bne $s0, $s1, Lbl1
add $s3, $s0, $s1
Lbl1: ...
Machine Format of bne:
op rs rt 16 bit offset I format
5 16 17 0x0001
Remember
After the bne instruction is fetched, the PC is updated so
that it is addressing the add instruction (PC = PC + 4).
The offset (plus 2 low-order zeros) is sign-extended and
added to the (updated) PC
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2004 Morgan Kaufmann Publishers
Another Instruction for Changing Flow
MIPS also has an unconditional branch instruction or jump
instruction:
j Lbl #go to Lbl
Example: if (i!=j)
h=i+j;
else
h=i-j;
beq $s0, $s1, Else

add $s3, $s0, $s1
j Exit
Else: sub $s3, $s0, $s1
Exit: ...

Assembling Jumps
Instruction:
j Lbl #go to Lbl
Machine Format:
op 26-bit address J format
2 ????
How is the jump destination address specified?

As an absolute address formed by
concatenating 00 as the 2 low-order bits to make it a
word address
concatenating the upper 4 bits of the current PC (now
PC+4)
Disassembling Jump Destinations
The low order 26 bits of the jump instr converted into a 32 bit jump
destination address by
concatenating two low-order zeros to create an 28 bit (word)
address and then concatenating the upper 4 bits of the current PC
(now PC+4) to create a 32 bit (word) address
that is put into the PC prior to the next Fetch cycle
from the low order 26 bits of the jump instruction Fetch

26 PC = PC+4
Exec Decode
00
32
4
PC 32

Branching Far Away
What if the branch destination is further away than can be captured
in 16 bits?
The assembler comes to the rescue it inserts

an unconditional jump to the branch target and
inverts the condition
beq $s0, $s1, L1
becomes
bne $s0, $s1, L2
j L1
L2:
Compiling a while loop in C
while (save[i]==k)
i+=1;
Loop: sll $t1, $s3,2

add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
add $s3, $s3, 1
j Loop
Exit:

Compiling While Loops
Compile the assembly code for the C while loop where i is in $s0, j
is in $s1, and k is in $s2
while (i!=k)
i=i+j;
Loop: beq $s0, $s2, Exit

add $s0, $s0, $s1
j Loop
Exit: . . .
Basic block A sequence of instructions without branches (except at

the end) and without branch targets (except at the beginning)

More Instructions for Making Decisions
We have beq, bne, but what about branch-if-less-than?
New instruction:
slt $t0, $s0, $s1 # if $s0 < $s1
# then
# $t0 = 1
# else
# $t0 = 0
Machine format:
set on less than (slt)
op rs rt rd funct R format
0 16 17 8 0 42 = 0x2a
2
Yet More Instructions for Making Decisions
Since constant operands are popular in comparisons, also have
slti
New instruction:
slti $t0, $s0, 10 # if $s0 < 10
# then
# $t0 = 1
# else
# $t0 = 0
Machine format:
op rs rt 16 bit number I format
a 16 8 0x000a
2
Other Branch Instructions
Can use slt, beq, bne, and the fixed value of 0 in $zero to
create all relative conditions
less than blt $s1, $s2, Lbl
less than or equal to ble $s1, $s2, Lbl
greater than bgt $s1, $s2, Lbl
great than or equal to bge $s1, $s2, Lbl
As pseudo instructions they are recognized (and expanded) by
the assembler
The assembler needs a reserved register ($at)
so there are policy of use conventions for registers
slt $at, $s1, $s2 #$at set to 1 if

bne $at, $zero, Lbl # $s1 < $s2

Another Instruction for Changing Flow
Most higher level languages have case or switch statements
allowing the code to select one of many alternatives depending on a
single value
Instruction:
jr $t1 #go to address in $t1

Machine format:
op rs funct R format
0 9 0 0 0 8 = 0x08
Compiling a Case (Switch) Statement
Memory
switch (k) {
case 0: h=i+j; break; /*k=0*/
case 1: h=i+h; break; /*k=1*/
case 2: h=i-j; break; /*k=2*/ L2
Assuming three sequential words in memory starting L1
at the address in $t4 have the addresses of the $t4
labels L0, L1, and L2 and k is in $s2 L0
add $t1, $s2, $s2 #$t1 = 2*k

add $t1, $t1, $t1 #$t1 = 4*k
add $t1, $t1, $t4 #$t1 = addr of JumpT[k]
lw $t0, 0($t1) #$t0 = JumpT[k]
jr $t0 #jump based on $t0
L0: add $s3, $s0, $s1 #k=0 so h=i+j
j Exit
L1: add $s3, $s0, $s3 #k=1 so h=i+h
j Exit
L2: sub $s3, $s0, $s1 #k=2 so h=i-j
Exit: . . .
Review: MIPS Instructions, so far
Category Instr OpCd Example Meaning
Arithmetic add 0 & 20 add $s1, $s2, $s3 $s1 = $s2 + $s3
(R & I format) subtract 0 & 22 sub $s1, $s2, $s3 $s1 = $s2 - $s3
add immediate 8 addi $s1, $s2, 4 $s1 = $s2 + 4

Data load word 23 lw $s1, 100($s2) $s1 = Memory($s2+100)
transfer
store word 2b sw $s1, 100($s2) Memory($s2+100) = $s1
(I format)
Cond. branch br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L
(I format) br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L
set on less than a slt $s1, $s2, 100 if ($s2<100) $s1=1; else $s1=0
immediate
(R format) set on less than 0 & 2a slti $s1, $s2, $s3 if ($s2<$s3) $s1=1; else $s1=0
Uncond. jump jump 2 j 2500 go to 10000

jump register 0 & 08 jr $t1 go to $t1

The MIPS instruction called set on less than
slt $t0, $s3, $s4

means that register $t0 is set to 1 if the
value in register $s3 is less than the value
in register $s4; otherwise, register $t0 is set
to 0.
slti $t0, $s2, 10

section 2.6
MIPS operands
32 registers $t 0, $t 1, , $t 7 Registers $s0 - $s7 map to 16-23 and $t0 - $t7 map to 8-15. MIPS register $zero
$zero always equals 0.
230memory Memory[4], , so sequential word addresses differ by 4. Memory holds data structures arrays,
words
Memory[4294967292] and spilled registers.

FIGURE 2.13 MIPS machine language revealed
through section 2.6.
add R 0 18 19 17 0 32 add $s1, $s2, $s3
sub R 0 18 19 17 0 34 sub $s1, $s2, $s3
lw I 35 18 17 100 lw $s1, 100($s2)
sw I 43 18 17 100 sw $s1, 100 ($s2)
and R 0 18 19 17 0 36 and $s1, $s2, $s3
or R 0 18 19 17 0 37 or $s1, $s2, $s3
nor R 0 18 19 17 0 39 nor $s1, $s2, $s3
andi I 12 18 17 100 andi $s1, $s2, 100
ori I 13 18 17 100 ori $s1, $s2, 100
sll R 0 0 18 17 10 0 sll $s1, $s2, 10
srl R 0 0 18 17 10 2 srl $s1, $s2, 10
beq I 4 17 18 25 beq $s1, $s2, 100
bne I 5 17 18 25 bne $s1, $s2, 100
slt R 0 18 19 17 0 42 slt $s1, $s2, $s3
j J 2 2500 j 10000 (see Section 2.9)
I-format I op rs rt address Data transfer, branch format
Policy of Use Conventions
Name Register number Usage
$zero 0 the constant value 0
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 return address
Register 1 ($at) reserved for assembler, 26-27 for operating system

Stored Program Concept
Instructions are bits

Programs are stored in memory
to be read or written just like data
memory for data, programs,

compilers, editors, etc.
Processor Memory
Fetch & Execute Cycle

Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Fetch the next instruction and continue

MIPS Organization
Processor
Memory
Register File
11100
src1 addr src1
5 32 data
src2 addr 32
5
registers
dst addr ($zero - $ra) read/write
5 src2
write data data addr
32 32 230
32 words
32 bits
br offset
32 Add
read data
32 PC 32 Add 32 32
32
4 write data 01100
Fetch 32
PC = PC+4 32 01000
4 5 6 7 00100
32 ALU 0 1 2 3
Exec Decode 00000
32
32 bits word address
32
(binary)
byte address
(big Endian)

So far:
Instruction Meaning
add $s1,$s2,$s3 $s1 = $s2 + $s3

sub $s1,$s2,$s3 $s1 = $s2 $s3
lw $s1,100($s2) $s1 = Memory[$s2+100]
sw $s1,100($s2) Memory[$s2+100] = $s1
bne $s4,$s5,L Next instr. is at Label if $s4 $s5
beq $s4,$s5,L Next instr. is at Label if $s4 = $s5
j Label Next instr. is at Label
Formats:
R op rs rt rd shamt funct
I op rs rt 16 bit address
J op 26 bit address

Constants
Small constants are used quite frequently (50% of operands)

e.g., A = A + 5;
B = B + 1;
C = C - 18;
Solutions? Why not?
put 'typical constants' in memory and load them.
create hard-wired registers (like $zero) for constants like one.
MIPS Instructions:
addi $29, $29, 4

slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4
Design Principle: Make the common case fast. Which format?

How about larger constants?
We'd like to be able to load a 32 bit constant into a register

Must use two instructions, new "load upper immediate" instruction
lui $t0, 1010101010101010

filled with zeros
1010101010101010 0000000000000000
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010 0000000000000000
0000000000000000 1010101010101010
ori
1010101010101010 1010101010101010

Assembly Language vs. Machine Language
Assembly provides convenient symbolic representation

much easier than writing down numbers
e.g., destination first
Machine language is the underlying reality
e.g., destination is no longer first
Assembly can provide 'pseudoinstructions'
e.g., move $t0, $t1 exists only in Assembly
would be implemented using add $t0,$t1,$zero
When considering performance you should count real instructions

Overview of MIPS
simple instructions all 32 bits wide

very structured, no unnecessary baggage
only three instruction formats
R op rs rt rd shamt funct
I op rs rt 16 bit address
J op 26 bit address
rely on compiler to achieve performance

what are the compiler's goals?
help compiler where we can

add R 0 18 19 17 0 32 add $s1, $s2, $s3
sub R 0 18 19 17 0 34 sub $s1, $s2, $s3
lw I 35 18 17 100 lw $s1, 100($s2)
sw I 43 18 17 100 sw $s1, 100 ($s2)
and R 0 18 19 17 0 36 and $s1, $s2, $s3
or R 0 18 19 17 0 37 or $s1, $s2, $s3
nor R 0 18 19 17 0 39 nor $s1, $s2, $s3
andi I 12 18 17 100 andi $s1, $s2, 100
ori I 13 18 17 100 ori $s1, $s2, 100
sll R 0 0 18 17 10 0 sll $s1, $s2, 10
srl R 0 0 18 17 10 2 srl $s1, $s2, 10
beq I 4 17 18 25 beq $s1, $s2, 100
bne I 5 17 18 25 bne $s1, $s2, 100
slt R 0 18 19 17 0 42 slt $s1, $s2, $s3
j J 2 2500 j 10000 (see Section 2.9)
I-format I op rs rt address Data transfer, branch format
2.7 Supporting Procedures in Computer
Hardware

Procedure: A stored subroutine that performs a
specific task based on the parameters with which it is
provided.
Jump-and-link instruction: An instruction that jumps
to an address and simultaneously saves the address
of the following instruction in a register ($ra in MIPS)
Return address: A link to the calling site that allows a
procedure to return to the proper address; in MIPS it is
stored in register $ra.
Program Counter (PC): The register containing the
address of the instruction in the program being
executed.

Caller: The program that instigates a procedure and
provides the necessary parameter values.
Callee: A procedure that executes a series of stored
instructions based on parameters provided by the
caller and then returns control to the caller.
Stack: A data structure for spilling registers
organized as a last-in-first-out queue.
Stack pointer: A value denoting the most recently
allocated address in a stack that shows where
registers should be spilled or where old register
values can be found.

The six steps of the execution of a procedure
1. Place parameter in a place where the procedure

can access them.
2. Transfer control to the procedure
3. Acquire the storage resources needed for the
procedure.
4. perform the desired task.
5. place the result value in a place where the calling
program can access it.
6. Return control to the point of origin, since a
procedure can be called from several points in a
program.

Registers for procedure calling:
$a0-$a3: four argument registers in which to

pass parameters
$v0-$v1: two value registers in which to
return values
$ra: one return address register to return to
the point of origin
$t0-$t9: 10 temporary registers that are not
preserved by the callee on a procedure call
$s0-$s7: 8 saved registers that must be
preserved on a procedure call

Compiling a C procedure(Doesnt Call Another)
Int leaf_example (int g, int h, int i, int j)

{ int f:
f=(g+h)-(i+j);
return f;}
leaf_example:
addi $sp, $sp, -12
sw $t1, 8($sp)
sw $t0, 4($sp)
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
add $v0, S0, $zero
lw $s0, 0($sp)
lw $t0, 4($sp)
lw $t1, 8($sp)
addi $sp, $sp, 12
jr $ra

Compiling a Recursive C Procedure
Int fact (int n)

{ if (n<1) return (1);
else return (n*fact(n-1));}
fact:
addi $sp, $sp, -8
sw $ra, 4($sp)
sw $a0, 0($sp)
slti $t0, $a0, 1
beq $t0, $zero, L1
addi $v0, $zero, 1
addi $sp, $sp, 8
jr $ra
L1: addi $a0, $a0, -1
jalfact
lw $a0, 0($sp)
lw $ra, 4($sp)
addi $sp, $sp, 8
mul $v0, $a0, $v0
jr $ra

FIGURE 2.14 The values if the stack pointer and the stack
(a) before, (b) during, and (c) after the procedure call

FIGURE 2.15 What is and what is not preserved across a
procedure call.
Preserved Not preserved

Saved registers: $s0 - $s7 Temporary registers: $t 0-$t 9
Stack pointer register: $sp Argument registers: $a0 - $a3
Return address register: $ra Return value registers: $v0 - $v1
Stack above the stack pointer Stack below the stack pointer

FIGURE 2.16 Illustration of the stack allocation (a)
before, (b) during, and (c) after the procedure call.

FIGURE 2.17 The MIPS memory allocation for program
and data.

FIGURE 2.18 MIPS register conventions.
Preserved on
Name Register number Usage call?
$zero 0 the constant value 0 n.a.
$v0-$v1 2-3 values for results and expression evaluation no
$a0-$a3 4-7 arguments no
$t0-$t7 8-15 temporaries no
$s0-$s7 16-23 saved yes
$t8-$t9 24-25 more temporaries no
$gp 28 global pointer yes
$sp 29 stack pointer yes
$fp 30 frame pointer yes
$ra 31 return address yes

section 2.7.
MIPS operands
$s0-$s7, $t 0- $t 9, Fast locations for data. In MIPS, data must be in registers to perform arithmetic.
32 registers $zero, $a0-a3, $v0-$v1, MIPS register $zero always equals 0. $gp (28) is the global pointer, $sp (29) is the
$gp, $fp, $sp, $ra stack pointer, $fp (30) is the frame pointer, and $ra (31) is the return address.
230memory Memory[4], , so sequential word addresses differ by 4. Memory holds data structures, arrays,
words
Memory[4294967292] and spilled registers, such as those saved on procedure calls.

Arithmetic
subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; Overflow detected
load word lw $s1, 100($s2) $s1 = Memory [$s2 + 100] Data from memory to register
Data transfer
store word sw $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Data from register to memory
Logical and immediate andi $s1, $s2, 100 $s1 = $s2 & 100 Bit-by-bit AND reg with constant
shift right logical srl $$s1, $s2, 10 $s1 = $s2 >> 10 Shift right by constant
branch on equal beq $s1, $s2, L if ($s1 == $s2) go to L Equal test and branch
branch on not bne $s1, $s2, L if ($s1 != $s2) go to L Not equal test and branch
equal
Condition
set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; Compare less than; used with beq,
al branch
else $s1 = 0 bne
set on less than slt $s1, $s2, 100 if ($s2 < 100) $s1 = 1; Compare less than immediate; used
immediate else $s1 = 0 with beq, bne
jump j L go to L Jump to target address

Unconditi
jump register jr $ra go to $ra For procedure return
onal jump
jump and link jal L $ra = PC + 4; go to L For procedure callKaufmann Publishers
2004 Morgan 94
add R 0 18 19 17 0 32 add $s1, $s2, $s3
sub R 0 18 19 17 0 34 sub $s1, $s2, $s3
lw I 35 18 17 100 lw $s1, 100($s2)
sw I 43 18 17 100 sw $s1, 100 ($s2)
and R 0 18 19 17 0 36 and $s1, $s2, $s3
or R 0 18 19 17 0 37 or $s1, $s2, $s3
nor R 0 18 19 17 0 39 nor $s1, $s2, $s3
andi I 12 18 17 100 andi $s1, $s2, 100
ori I 13 18 17 100 ori $s1, $s2, 100
sll R 0 0 18 17 10 0 sll $s1, $s2, 10
srl R 0 0 18 17 10 2 srl $s1, $s2, 10
beq I 4 17 18 25 beq $s1, $s2, 100
bne I 5 17 18 25 bne $s1, $s2, 100
slt R 0 18 19 17 0 42 slt $s1, $s2, $s3
j J 2 2500 j 10000 (see Section 2.9)
jr R 0 31 0 0 0 8 jr $ra
jal J 3 2500 jal 10000 (see section 2.9)
I-format I op rs rt address Data transfer, branch
2004 formatPublishers
Morgan Kaufmann 95
2.8 Communicating with People

Instructions to move bytes
lb $t0, 0($sp); Loads a byte from

memory, placing it in the rightmost 8
bits of a register.
sb $t0, 0($gp); Stores a byte from the
rightmost 8 bits of a register, placing it
to memory.

FIGURE 2.21 ASCII representation of characters.
ASCII Char- ASCII Char- ASCII Char- ASCII Char- ASCII Char- ASCII Char-
value acter value acter value acter value acter value acter value acter
32 space 48 0 64 @ 80 P 96 ` 112 p
33 ! 49 1 65 A 81 Q 97 a 113 q
34 50 2 66 B 82 R 98 b 114 r
35 # 51 3 67 C 83 S 99 c 115 s
36 $ 52 4 68 D 84 T 100 d 116 t
37 % 53 5 69 E 85 U 101 e 117 u
38 & 54 6 70 F 86 V 102 f 118 v
39 55 7 71 G 87 W 103 g 119 w
40 ( 56 8 72 H 88 X 104 h 120 x
41 ) 57 9 73 I 89 Y 105 I 121 y
42 * 58 : 74 J 90 Z 106 j 122 z
43 + 59 ; 75 K 91 [ 107 k 123 {
44 , 60 < 76 L 92 \ 108 l 124 |
45 - 61 = 77 M 93 ] 109 m 125 }
46 . 62 > 78 N 94 ^ 110 n 126 ~
47 / 63 ? 79 O 95 _ 111 o 127 DEL

2.9 MIPS Addressing for 32-Bits Immediates
and Addresses

FIGURE 2.23 The effect of the lui instruction.
The machine language version of lui $t0, 255 # $t0 is register 8:
001111 00000 01000 0000000011111111
Contents of register $t0 after executing lui $t0, 255:
0000 0000 1111 1111 0000000011111111

Loading a 32-bit Constant
Load 0000 0000 0011 1101 0000 1001 0000

0000 to register $s0
lui $s0, 61 #61 decimal = 0000 0000 0011 1101

ori $s0, $s0, 2304 #2304 decimal = 0000 1001
0000 0000

MIPS Addressing Mode Summary
1. Register addressing,
2. Base or displacement
addressing,
3. Immediate addressing,
4. PC-relative addressing,
5. Pseudodirect addressing,

FIGURE 2.24 Illustration of the five MIPS addressing modes.
1. Immediate addressing
op rs rt Immediate
2. Register addressing
op rs rt rd ... funct Registers
Register
3. Base addressing
op rs rt Address Memory
Register + Byte Halfword Word
4. PC-relative addressing
op rs rt Address Memory
PC + Word
5. Pseudodirect addressing
op Address Memory
PC Word

FIGURE 2.25 MIPS instruction encoding
Op (31:26)
28-26 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111)
31-29
0(000 R-format Bltz/gez jump Jump & branch branch blez bgtz
) link eq
1(001 add addiu set less sltiu andi ori xori load upper
) immediate than imm
imm.
2(010 TLB FLPt
)
3(011)
4(100 load byte load half lw1 load word lbu lhu lwr
)
5(101 store byte store sw1 store word swr
) half
6(110) lwc0 lwc1
7(111) swc0 swc1 2004 Morgan Kaufmann Publishers 104
Op (31:26)=010000 (TLB), rs(25:21)
23-21 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111)
25-24
0(00) mfc0 cfc0 mtc0 ctc0
1(01)
2(10)
3(11)

Op (31:26)=000000 (R-format), funct(5:0)
2-0 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111)
53
0(000 shift left shift right sra sllv srlv srav
) logical logical
1(001 jump reg. jalr syscall break
)
2(010 mfhi mthi mflo mtlo
)
3(011) mult multu div divu
4(100 add addu subtract subu and or xor not or (nor)
)
5(101 set l . t . sltu
)
6(110)
7(111)
FIGURE 2.26 MIPS instruction formats in Chapter 2.
Name Fields Comments

R-format op rs rt rd shamt funct Arithmetic instruction format
I-format op rs rt address/immediate Transfer, brance, imm. format
J-format op target address jump instruction format

FIGURE 2.27 MIPS assembly language revealed in
Chapter 2.
MIPS operands
$s0-$s7, $t 0- $t 9, Fast locations for data. In MIPS, data must be in registers to perform arithmetic.
32 registers $zero, $a0-a3, $v0-$v1, MIPS register $zero always equals 0. Register $at is reserved for the assembler to
$gp, $fp, $sp, $ra, $at handle large constants.
memory
Memory[4], , so sequential word addresses differ by 4. Memory holds data structures, arrays,
words
Memory[4294967292] and spilled registers, such as those saved on procedure calls.

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; Overflow detected
add immediate addi $s1, $s2, 100 $s1 = $s2+ 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory [$s2 + 100] Word from memory to register
store word sw $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Word from register to memory
load half lh $s1, 100($s2) $s1 = Memory [$s2 + 100] Halfword memory to register
Data transfer store half sh $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Halfword register to memory
load byte lb $s1, 100($s2) $s1 = Memory [$s2 + 100] Byte from memory to register
store byte sb $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Byte from register to memory
load upper immed. lui $s1, 100 $s1 = 100 * 2^16 Loads constant in upper 16 bits
Logical and immediate andi $s1, $s2, 100 $s1 = $s2 & 100 Bit-by-bit AND reg with constant
shift right logical srl $$s1, $s2, 10 $s1 = $s2 >> 10 Shift right by constant

Continue..
branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to Equal test; PC-relative branch
PC+4+100
branch on not bne $s1, $s2, 25 if ($s1 != $s2) go to L Not equal test; PC-relative
equal PC+4+100
Condition
al branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; Compare less than; for beq, bne
else $s1 = 0
set on less than slt $s1, $s2, 100 if ($s2 < 100) $s1 = 1; Compare less than constant
immediate else $s1 = 0
jump j 2500 go to 10000 Jump to target address
Unconditi
jump register jr $ra go to $ra For procedure return
onal jump
jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call

2.10 Translating and Starting a Program

Pseudoinstruction: A common variation of assembly language
instructions often treated as if it were an instruction in its own
right.
Symbol table: A table that matches names of labels to the
addresses of the memory words that instructions occupy.
Linker Also called link editor: A systems program that
combines independtly assembled machine language programs
and resolves all undefined labels into an executable file.
Executable file: A functional program in the format of an object
file that contains no unresolved references, relocation
information, symbol table, or debugging information.
Loader: A systems program that places an object program in
main memory so that it is ready to execute.

FIGURE 2.28 A translation hierarchy for C.

FIGURE 2.29 Dynamically linked library via lazy
procedure linkage.

FIGURE 2.30 A translation hierarchy for JAVA.

2.16 Real Stuff: IA-32 Instructions

Alternative Architectures
Design alternative:
provide more powerful operations
goal is to reduce number of instructions executed
danger is a slower cycle time and/or a higher CPI
The path toward operation complexity is thus fraught with peril.

To avoid these problems, designers have moved toward simpler
instructions
Lets look (briefly) at IA-32

IA - 32
1978: The Intel 8086 is announced (16 bit architecture)

1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits, +instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)
1997: 57 new MMX instructions are added, Pentium II
1999: The Pentium III added another 70 instructions (SSE)
2001: Another 144 instructions (SSE2)
2003: AMD extends the architecture to increase address space to 64 bits,
widens all registers to 64 bits and other changes (AMD64)
2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds
more media extensions
This history illustrates the impact of the golden handcuffs of compatibility

adding new features as someone might add clothing to a packed bag
an architecture that is difficult to explain and impossible to love

IA-32 Overview
Complexity:
Instructions from 1 to 17 bytes long
one operand must act as both a source and destination
one operand can come from memory
complex addressing modes
e.g., base or scaled index with 8 or 32 bit displacement
Saving grace:
the most frequently used instructions are not too difficult to
build
compilers avoid the portions of the architecture that are slow
what the 80x86 lacks in style is made up in quantity,

making it beautiful from the right perspective

IA-32 Registers and Data Addressing
Registers in the 32-bit subset that originated with 80386
Name Use
31 0
EAX GPR 0
ECX GPR 1
EDX GPR 2
EBX GPR 3
ESP GPR 4
EBP GPR 5
ESI GPR 6
EDI GPR 7
CS Code segment pointer
SS Stack segment pointer (top of stack)
DS Data segment pointer 0
ES Data segment pointer 1
FS Data segment pointer 2
GS Data segment pointer 3
EIP Instruction pointer (PC)
EFLAGS Condition codes

IA-32 Register Restrictions
Registers are not general purpose note the restrictions below

IA-32 Typical Instructions
Four major types of integer instructions:

Data movement including move, push, pop
Arithmetic and logical (destination register or memory)
Control flow (use of condition codes / flags )
String instructions, including string move and string compare

IA-32 instruction Formats
Typical formats: (notice the different lengths)

a. JE EIP + displacement
4 4 8
JE Condi- Displacement
tion
b. CALL
8 32
CALL Offset
c. MOV EBX, [EDI + 45]

6 1 1 8 8
r/m
MOV d w Displacement
Postbyte
d. PUSH ESI
5 3
PUSH Reg
e. ADD EAX, #6765

4 3 1 32
ADD Reg w Immediate
f. TEST EDX, #42

7 1 8 32
TEST w Postbyte Immediate

Summary
Instruction complexity is only one variable

lower instruction count vs. higher CPI / lower clock rate
Design Principles:
simplicity favors regularity
smaller is faster
good design demands compromise
make the common case fast
Instruction set architecture
a very important abstraction indeed!

Our First Example
Can we figure out the code?
swap(int v[], int k);

{ int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp;
} swap:
muli $2, $5, 4
add $2, $4, $2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31

MIPS

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Instruction Set Design - Goals

2004 Morgan Kaufmann Publishers 1

MIPS, Sun SPARC, IBM PowerPC

Instruction sets are measured by how well compilers use them as

CISC (C for complex), e.g., Intel x86

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(MIPS: Microprocessors without Interlocked

Four design principles guide

Language of the Machine

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Stored-Program Concept : The idea that

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All instructions have 3 operands

MIPS code: add a, b, c

(well talk about registers in a bit)

The natural number of operands for an operation like addition is

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MIPS assembly language

Arithmetic add add a, b, c a=b+c Always three operands

subtract sub a, b, c a=b-c Always three operands

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Design Principle: simplicity favors regularity.

MIPS code: add a, b, c

Operands must be registers, only 32 registers provided

Design Principle: Smaller is faster. Why?

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add t0, $s1, $s2

sub $t0, $s1, $s2

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Arithmetic instructions operands must be registers,

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Viewed as a large, single-dimension array, with an address.

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Assuming variable b is stored in $s2 and that the base address of

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Load and store instructions

C code: A[12] = h + A[8];

MIPS code: lw $t0, 32($s3)

Can refer to registers by name (e.g., $s2, $t2) instead of number

Cant write: add 48($s3), $s2, 32($s3)

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How do we make this work?

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MIPS immediate instructions

addi $s3, $s3, 4 #$s3 = $s3 + 4

There is no subi instruction, can you guess why not?

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Category Instr Example Meaning

Arithmetic add add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3

add immediate addi $s1, $s2, 4 $s1 = $s2 + 4

Data load word lw $s1, 32($s2) $s1 = Memory($s2+32)

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