Chapter 2 Op Amp

Course Outline
Text Book
Microelectronics Circuits
By Sedra & Smith (5th/6th Ed)
Topics
Op Amps
Ch 2
Filters
Ch 12
Oscillators
Ch 13
Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
Chapter #2:
Signals and
Amplifiers
from Microelectronic
Circuits Text
by Sedra and Smith
Oxford Publishing
(0195323033)
Introduction
IN THIS CHAPTER YOU WILL LEARN

The terminal characteristics of the ideal op-
amp.
How to analyze circuits containing op-
amps, resistors, and capacitors.
How to use op-amps to design amplifiers
having precise characteristics.

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Introduction
IN THIS CHAPTER YOU WILL LEARN

How to design more sophisticated op-amp
circuits, including summing amplifiers,
instrumentation amplifiers, integrators, and
differentiators.
Important non-ideal characteristics of op-
amps and how these limit the performance
of basic op-amp circuits.

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Introduction
You have studied and understood (Hopefully)
What is an amplifier?
Gain......Voltage, Current, Inverting, non-inverting
Response.......Time, Frequency
Impedance.....Input, Output

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Amplifier Types
Gain Transfer
Description Symbol Function
Voltage Amplifier
or Av vo/vin
Voltage Controlled Voltage Source (VCVS)
Current Amplifier
or Ai io/iin
Current Controlled Current Source (ICIS)
Transconductance Amplifier gm
or io/vin
Voltage Controlled Current Source (VCIS) (siemens)
Transresistance Amplifier rm
or vo/iin
Current Controlled Voltage Source (ICVS) (ohms)

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Operational
Amplifier
Usually Called Op Amps

An amplifier is a device that accepts a varying input signal and
produces a similar output signal with a larger amplitude.
Usually input and output are connected so part of the output is fed
back to the input. (Feedback Loop)
Most Op Amps behave like voltage amplifiers. They take an input
voltage and output a scaled version.
They are the basic components used to build analog circuits.
The name operational amplifier comes from the fact that they
were originally used to perform mathematical operations such as
integration and differentiation.
Integrated circuit fabrication techniques have made high-
performance operational amplifiers very inexpensive in comparison
to older discrete devices

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Op Amp
circuit
Symbols for
Ideal and Real
Op Amps
OpAmp uA741
LM111 LM324
2.1.1. The Op
Amp Terminals
terminal #1
inverting input
terminal #2
non-inverting input
terminal #3
output
terminal #4
positive supply VCC
terminal #5
negative supply VEE

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and
Characteristics
of Ideal Op
Amp
ideal gain is defined below
v3 A(v2 v1)
ideal input characteristic is infinite impedance

ideal output characteristic is zero impedance
differential gain (A) is infinite
bandwidth gain is constant from dc to high
frequencies
Q: But, is an amplifier with infinite gain of

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and
Characteristics
of Ideal Op
Amp
ideal gain: is defined below
v3 A(v2 v1)
ideal input characteristic: infinite impedance
ideal output characteristic: zero impedance

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and
Characteristics
of Ideal Op-
Amp
An amplifiers input is composed of two
components
differential input (vdf) is difference
between inputs at inverting and non-
inverting terminals
common-mode input (vcmi) is input
common-mode differential
present at both inverting inputand
(vcmi ) non-inverting
64 7 48 678
input (vdf )
terminals

v 10 1 10 1 10 10 1 1
in

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and
Characteristics
of Ideal Op-
Amp
Similarly, two components of gain exist
differential gain (A) gain applied to
differential input ONLY
common-mode gain (Acm) gain applied
to common-mode input ONLY
common-mode differential
e.g. v1 101 e.g. v2 101 output output
64 4 7 4 48 6 4 4 7 4 48 6 44 7 4 48 64 7 48
vout Acm10 A1 Acm10 A1 Acm 10 10 A 1 1

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and
Characteristics
of Ideal Op
Amp
Table 2.1: Characteristics of Ideal Op
Amp
infinite input impedance
zero output impedance
zero common-mode gain (Acm = 0)
complete common-mode rejection
infinite open-loop gain (A = infinity)
infinite bandwidth
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2.1.3.
Differential &
Common-Mode
Signals
Q: How is common-mode input (vcmi)

defined in terms of v1 and v2?
6 4inverting
47 4 input
48
6common-mode
44 7 4 input
48 v1 vcmi vdi / 2
1 {
vcmi (v1 v2) but also... diff
2 v2 vcmi vdi / 2
1 4 4 2 4 43
non-inverting input

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2.1.3.
Differential &
44Common-Mode
6common-mode
7 4 input
48
1 Signals
vcmi (v1 v2)
2
but also...
6 4inverting
47 4 input
48
v1 vcmi vdi / 2
{
diff
v2 vcmi vdi / 2
1 4 4 2 4 43
non-inverting input

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Typical Op Amp
Parameters
Parameter Variable Typical Ideal

Ranges Values
Open-Loop A 105 to 108
Voltage

Gain
Input Ri 105 to 1013
Resistance

Output Ro 10 to 100 0
Resistance
Supply Vcc/V+ 5 to 30 V N/A
Voltage -Vcc/V- -30V to 0V N/A
How to Find
These Values
Component Datasheets
Many manufacturers have made these freely
available on the internet
Example: LM 324 Operational Amplifier
dB
Decibels
Since P = V2/R
10 log (P/Pref) or 20 log (V/Vref)
In this case:
20 log (Vo/Vin) = 20 log (A) = 100
A = 105 = 100,000
Large Signal
Voltage Gain = A
Typical
A = 100 V/mV = 100V/0.001V = 100,000
Minimum
A = 25 V/mV = 25 V/0.001V = 25,000
Caution A is
Frequency
Dependent
Some
Specifications
Open loop gain (AoL ): Usually several thousand.

Input offset voltage ( Vos): Small, usually a few millivolts.
Input offset current (Ios ): Usually between a few and several
hundred nanoamps.
Input resistance ( Rin):Typically greater than one megohm, but
it can be as high as several hundred megohms.
Output resistance (Rout ): Usually less than a few hundred
ohms.
Slew rate ( S ): The maximum rate of output voltage change
given in volts per microsecond.
CMRR = Ad/Acm

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Open Circuit
Output Voltage
v o = A vd
Ideal Op Amp
vo = (vd)
Open Circuit
Output Voltage
Real Op Amp
Voltage Output
Range Voltage
Positive A vd > V + vo ~ V+
Saturation
Linear Region V- < A v d < vo = A vd
V+
Negative A vd < V - vo ~ V-
Saturation
The voltage produced by the dependent voltage source inside the op amp
is limited by the voltage applied to the positive and negative rails.
Voltage Transfer
Characteristic
Range where
we operate
the op amp
as an
amplifier.
vd
Ideal Op Amp
Because Ri is equal
to , the voltage
across Ri is 0V.
i2 = 0
v v1 = v2
2
vd = 0 V
i1 = 0
v
1
Almost Ideal Op
Amp
Ri =
Therefore, i1 = i2 = 0A
Ro = 0
Usually, vd = 0V so v1 = v2
The op amp forces the voltage at the inverting input terminal
to be equal to the voltage at the noninverting input terminal
if there is some component connecting the output terminal to
the inverting input terminal.
Rarely is the op amp limited to V- < vo < V+.
The output voltage is allowed to be as positive or as negative
as needed to force vd = 0V.
Example #1:
Voltage
Comparator
is = 0 i1 = 0
i2 = 0
Note that the inverting input and non-inverting

input terminals have rotated in this schematic.
Example #1
(cont)
The internal circuitry in the op amp tries to force the

voltage at the inverting input to be equal to the non-
inverting input.
As we will see shortly, a number of op amp circuits
have a resistor between the output terminal and
the inverting input terminals to allow the output
voltage to influence the value of the voltage at the
inverting input terminal.
Example #1:
Voltage
Comparator
is = 0 i1 = 0
i2 = 0
When Vs is equal to 0V, Vo = 0V.

When Vs is smaller than 0V, Vo =
V+.
When Vs is larger than 0V, Vo =
Electronic
Response
Given how an op amp functions, what do you expect

Vo to be if
V2 = 5V when:
1. Vs = 0V?
2. Vs = 5V?
3. Vs = 6V?
Electronic
Response
Given how an Op Amp functions and A= 103, what do

you expect third voltage, Vicm, and Vid?
1. V2=0v and Vo =2v
2. V2=5v and Vo=-10v
3. V1=1.002v and V2=0.998v
4. V1=-3.6v and Vo=-3-6v
2.2. The
Inverting
Configuration
Q: What are two basic closed-loop op-amp

configurations which employ op-amp and
resistors alone?
A: 1) inverting and 2) non-inverting op
amp

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2.2.The
Figure 2.5: Theinverting closed-loop configuration.
Inverting
R2 facilitates
Configuration
negative
feedback
R1 regulates
question: whatlevel
are two basic closed-loop op amp
of this feedback
configurations which employ op-amp and resistors alone?
answer: inverting and non-inverting op amp
note: here we examine the inverting type
non-inverting
input is grounded
source is applied
to inverting
Microelectronic input
Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.2.1.
Closed-Loop
Gain
Q: How does one analyze closed-

loop gain for inverting
configuration of an ideal op-amp?
step #1: Begin at the output
terminal
step #2: If vOut is finite, then
6 because
4 4 7A in4infi4 8
nite
differential input must equal 0 vOut
virtual short circuit btw v1 v2 v1 0
{A
and v2
virtual ground exists at v1

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2.2.1.
Closed-Loop
Gain
step #3: Define current in to inverting input

(i1).
step #4: Determine where this current
flows?
refer to followingground slide
virtual
}
(vIn) (v1) vIn 0 vIn
i1
R1 R1 R1

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2.2. The
FigureInverting
2.5: The inverting closed-loop configuration.
Configuration
i1
question: what are two basic closed-loop op amp
configurations which employ op-amp and resistors alone?
answer:
1 i
inverting and non-inverting op-amp i=
note: here we examine the inverting type
0

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2.2.1.
Closed-Loop
Gain
step #5: Define vOut virtual

ground
in terms of current }
vOut (v1) (i1R2) i1R2
flowing across R2.
step #6: Substitute R2
vOut vIn
vin / R1 for i1. R1
solution
note: this expression is one of the

fundamentals of electronics
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2.2.1.
Figure 2.6: Analysis of the inverting configuration.
Closed-Loop
The circled numbers indicate the order of the analysis
Gain steps.
question: how will we

step #4: define vOut in closed-loop
terms of current flowing
across R2 gain
step #5: substitute vin / R1 G=
for i1.
-R2/R1

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2.2.2. Effect of
Finite Open-
Loop Gain
Q: How does the gain expression change if

open loop gain (A) is not assumed to be
infinite?
A: One must employ analysis similar to
the previous, result is presented GA below
}
vOut R2 / R1 R2
GA
vIn 1 (R2 / R1) R1
1
1 4 4 2 A 4 4 3
if A then the previous
gain expression is yielded
non-ideal Oxford University Publishing
ideal gain
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2.2.2 The Effect of Finite Open-
Loop Gain (A)
I ( 0 / A) I 0 / A
i1
R1 R1
0 0 / A
0 i1 R2 0 I R2
A A R1
0 R2 / R1
G (2.5)
I 1 (1 R2 / R1 ) / A
2 1 0 1 1 0 / A
1 0 / A
Microelectronic Circuits - Fifth Edition Sedra/Smith

2.2.2. Effect of
Finite
Open-Loop
Gain
Q: Under what condition can G = -R2 / R1

be employed over the more complex
expression?
A: If 1 + (R2/R1) << A, then simpler
expression may be used.
R R R / R
if 1 2
A then GA 2
else GA 2 1
R1 R1 1 (R2 / R1)
1
A
ideal gain Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith non-ideal
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Example 2.1:
Simple Inverting
Amplifier
Problem Statement: Consider an inverting

configuration with R1 = 1kOhm and R2 =
100kOhm.
Q(a): Find the closed-loop gain (G) for the cases
below. In each case, determine the percentage
error in the magnitude of G relative to the ideal
value.
cases are A = 103, 104, 105
Q(b): What is the voltage v1 that appears at the
inverting input terminal when vIn = 0.1V.
Q(c): If the open loop gain (A) changes from 100k
to 50k, what is percentage change in gain (G)?
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EXAMPLE 2.1
(a ) R1 1 k, R2 100 k, A=10 3 ,10 4 ,10 5 , % error of G to ideal G= ?

I 0.1 V
(b) A changes from 100,000 to 50,000 (50% reduction),
% change of G = ?
G ( R2 / R1 )
100
( R2 / R1 )
10
3
10
4
10
5

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2.2.3. Input
and Output
Resistances
Q: What is input resistance for inverting op-amp?

How is it defined mathematically?
A: R1 (refer to math below)
Q: What does this say?
A: That, for the combination of ideal op-amp
and external resistors, input resistance will be
action:
this assumes finite that 7 4 48 6simplify
action: simplify
6 44 78
ideal op-amp and v vIn v
Ri In In R1
external resistors i{In (vIn v { 1 )/ R1 vIn / R1
are considered same virtual
as i1 ground
one unit
0
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2.2.3. Input
and Output
Resistances
Rout is found by applying a test
current (or voltage) source to the
amplifier output and determining
the voltage (or current) after
turning off all independent
sources. Hence,
vo i v
Rs =
i 0R
2 2 11
But i1=i2
vo i (R R )
1 2 1
v Since v- = 0, i1=0.
R s R sincev 0
in i 1 Therefore vo = 0
s
Rout
irrespective of the
0 value of
io .
2.2.3 Input and output Resistance of Inverting Amplifier
(not op-amp)
What would happen if R1 is too small
?
R
R2
G
( R R1 )
Therefore, input resistance R1 should
be much larger than output resistance
Ideal input I I of previous stage. Unfortunately, the
resistance of i iR R1 internal resistance of most sensors are
/ R
inverting 1 I 1
large.
amplifier, not op-
For high amp.
gain (- R2 / R1), we need
small R1, otherwise, R2 would be Contradictio
impractically large. n!
Solution: example
2.2
Microelectronic Circuits - Fifth Edition Sedra/Smith 50
Example 2.2:
Another
Inverting Op-
Amp
Problem Statement: Consider
the circuit below...
Q(a): Derive an expression for
the closed-loop gain vOut/vIn of
this circuit.
Q(b): Use this circuit to design
an inverting amplifier with gain
of 100 and input resistance of
1Mohm.
Assume that one cannot use
any resistor with resistance Figure 2.8: Circuit for Example
larger than 1Mohm. 2.2. The circled numbers
Q(c): Compare your design indicate the sequence of the
with that based on traditional
Oxford University Publishing steps in the analysis.
inverting configuration.
Microelectronic Circuits by Adel S. Sedra
(0195323033)
and Kenneth C. Smith
EXAMPLE 2.2 (a) Find 0 / I . (b) Design the inverting amplifier with
(a gain of 100 and an input resistance
0 0 1 M.
) 0
A
I I 0 I
i1
R R R
I
i2 i
R
I R
x i2 R2 0 R2 2 I
R R
0 x R2
i3
R3 R2 R3 I
R
i4 i 2 i 3 I 2 I
R R1 R3 (b input resistance 1 R1=1
0 x i4 R4 ) maximum M M
resistance in practical
circuits:
R2, R4=1 1 M
R2 R
= I I 2 I R4 gain of R =10.2 kM
R1 R R1 R3 3
-100
0 R R4 R4 (If we adopt a typical inverting amplifier
2 1 and
R2=100 M, impractically large !) R1=1 M,
I R1 R2 R3
52
2.2.4. An
Important
Application
The Weighted
Summer
weighted summer - is a closed-loop
amplifier configuration which provides an
output voltage which is weighted sum of
the inputs.
Figure 2.10: A
weighted summer.

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Summing Amplifier
The output voltage in summing amplifier is
vo=-if*Rf since vi=0
iA if
iB
+
vi
-
Summing Amplifier
The output voltage in summing amplifier is
vo=-if*Rf since vi=0
if=iA+iB=vA/RA+vB/RB => vo=-(vA/RA+vB/RB)*Rf

iA if
For n inputs we will have
vo=- Rf i(vi/Ri)
iB
+
vi
-
Exercise
Find the currents and voltages in these two circuits:
a) i1=vin/R1=1V/1k=1mA
i2=i1=1mA from KCL

vo=-i2*R2=-10V from KVL
io=vo/RL=-10mA from Ohms
law
ix=io-i2=-10mA-1mA=-11mA
Exercise
Find the currents and voltages in these two circuits:
b) i1=vin/R1=5mA
i2=i1=5mA
i2*1k= i3*1k => i3=5mA
i4=i2+i3=10mA
vo=- i2*1k- i4*1k=-10 V

Exercise
Find expression for the output voltage in the amplifier circuit:

i2
i5
i1
i3
+ iL
i4
V3 i1=v1/R1=v1/10k
i2=i1=v1/10mA
-
v3 =- i2*R2=- v1/10k *20k =-2v1
Exercise
Find expression for the output voltage in the amplifier circuit:

v3 =- i2*R2=- v1/10k *20k =-2v1
i5=i3+i4=v3/10k +v2/10k
vo =- i5*R5=-(v3/10k +v2/10k )*20k =-2v3 -2v2 =4v1 -2v2

i2
i5
i1
i3
+ iL
V3
i4
-
Positive Feedback
When we flip the polarization of the op-amp as shown on the

figure we will get a positive feedback that saturates the
amplifier output.
This is not a good idea.
2.3. The
Non-Inverting
Configuration
non-inverting op-amp configuration

is one which utilizes external resistances
(like the previous) to effect voltage gain.
However, the polarity / phase of the output
is same as input.

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2.3. 2.12:
Figure The Non-
The non-inverting configuration.
Inverting R1 and R2 act as voltage
Configurationdivider, regulating negative
feedback to the inverting
input
inverting
input is
grounded
through R1
node
#1
node
#2
source is applied
Oxford University Publishing to non-inverting
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2.3 The Non-inverting
2.3.1 The close-Loop Configuration
Gain
The inverting configuration.
Figure 2.12 The noninverting the Role of Negative

configuration. feedback
Lets derive the expression of the 1. Let I increase.
voltage gain. 2. Id is increased.
0 R2 3. o is increased.
1 (2.9)
I R1 4. Fraction of o will be fed back to (-)
5. This feedback will counteract the
terminal.
Another derivation increase in Id , driving back to zero.
o is divided to R1 and R2. degenerative feedback
R1
1 0 (2.10)
R1 R2 63
Finite Open-loop Gain and Gain
Error
vo Av A(vs v ) A(vs vo )
id 1
vo A
Av
v s 1 A
1 R
Av 1 2
R
1
R
v 1 v v This is the ideal voltage
1 R R o o
1 2 gain of the amplifier. If A
R is not >>1, there will be
1 is called the
Gain Error.
R R feedback
1 2
factor.
Gain Error is given by
GE = (ideal gain) - (actual gain)
For the non-inverting amplifier,1
GE
A

1
1 A (1 A )
Gain error is also expressed as a

fractional or percentage error.
1 A

FGE 1 A
1 1

1 1 A A

1
PGE 100%
A
2.3.2 Characteristics of the noninverting Configuration
0 R
1 2 > 0 - Input and output signals have same phase.-
I R1
- Input impedance is infinite.noninverting.
- output impedance is zero.
2.3.3 Effect of Finite Open-

- Follow the procedureLoop Gain
used for inverting
amplifier.
0 1 ( R2 / R1 )
G (2.11) - non-inverting
- denominators are I 1 ( R2 / R1 )
1 amplifier
identical ! A
How come? 0 R2 / R1
G (2.5) - inverting
I (1 R2 / R1 )
identical negative 1 amplifier
A
feedback
(think about 0 V - numerators are different amount of
input !) different ! feedback (closed loop
How come? gain)
In order to minimize the effect of the finite

R2 open-loop gain,
A ? 1+ (2.12)
R1
Microelectronic Circuits - Fifth Edition Sedra/Smith 66

Characteristics of Non-Inverting
Op-Amp Configuration
vOut
vIn
R } R 1 (R2 / R1)
ideal gain A 1 2 : GA 1 2
R1 R1 1 1 (R2 / R1)
A
1 (R2 / R1)
non-ideal gain: .G
{A
1 (R2 / R1)
vOut 1
vIn A
1 (R2 / R1) 1 (R2 / R1)
percent gainerror: pge 100
A 1 (R2 / R1) 1 1 (R2 / R1)
A
R1 1 (R2 / R1)
invertinginputpotential: .v1 vOut 1 (R / R )
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith R1 R2 1 2 1
(0195323033)
Configuration and Characteristics
of Buffer / Voltage-Follower Op-
Amp Configuration
Figure 2.14: (a) The unity-gain buffer or follower

amplifier. (b) Its equivalent circuit model.
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Configuration and Characteristics
Main point? For the buffer amp, output
of Buffer / Voltage-Follower Op-
voltage is equal (in both magnitude and
Amp Configuration
phase) to the input source. However, any
current supplied to the load is drawn from
amplifier supplies (VCC, VEE) and not the input
source (vI).
Figure 2.14: (a) The unity-gain buffer or follower

amplifier. (b) Its equivalent circuit model.
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The Unity-Gain Amplifier or Buffer
This is a special case of the non-inverting amplifier,

which is also called a voltage follower, with infinite
R1 and zero R2.
Hence Av = 1.
It provides an excellent electrical isolation while
maintaining the signal voltage level.
The ideal buffer requires no input current and can
drive any desired load resistance without loss of
signal voltage.
Such a buffer is used in many sensor and data
Unity-Gain Buffer
Closed-loop voltage gain
vi v v vo
vo
AF 1
vi
Used as a "line driver" that transforms a high input impedance (resistance) to

a low output impedance. Can provide substantial current gain.
2.4. Difference
Amplifiers
difference amplifier is a closed-loop

configuration which responds to the difference
between two signals applied at its input and
ideally rejects signals that are common to the
two.
Ideally, the amp will amplify only the
differential signal (vdf) and reject completely
the common-mode input signal (vcmi).
However, a practical circuit will behave as
below
vOut Avdf Acmvcmi
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2.4. Difference
Amplifiers
common-mode
input
common-mode
gain
differential input
differential gain
vOut Avdf Acmvcmi

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2.4. Difference
Amplifiers
common-mode rejection ratio (CMRR)

is the degree to which a differential
amplifier rejects the common-mode
input.
Ideally, CMRR = infnity
A
CMRR 20 log10
ACm

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2.4. Difference
Figure 2.15: Representing the input signals to a
Amplifiers
differential amplifier in terms of their differential and
common-mode components.
ADi
CMMR 20 log10
ACm

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2.4. Difference
Amplifiers
Q: The op amp itself is differential in

nature, why cannot it be used by itself?
A: It has an infinite gain, and therefore
cannot be used by itself. One must
devise a closed-loop configuration which
facilitates this operation.

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2.4.Figure
Difference
2.16: A difference amplifier.
Amplifiers

(0195323033)
Difference Amplifier
I/P Current to op amp is zero
v v
v1 v
i1
R1
v v0
i1
R2
v1 v v v0

R2 R1 R2
v v2
R1 R2 R2 R2
v1 v2 v2 v0
R1 R2 R R2
1
R1 R2
Difference Amplifier
R2 R2
v1 v2 v2 v0
R1 R2 R R2
1
R1 R2
R2 R2 R22
v0 v1 v2 v2
R1 R1 R2 R1 R1 R2
R2 R2 R2 R2
v0 v1
R1 R2
1 v2 v0 v2 v1
R1 R1 R1
2.4.1. A Single
Op-Amp
Difference
Amp
Q: What are the characteristics of the
difference amplifier?
A: Refer to following equations
(R2 R1)R4 R2
vOut vIn2 vIn1
(R4 R3)R1 R1
R1 R 3 R2
but if then vOut vIn2 vIn1
R2 R 4
R1
(0195323033)
A Shift in
Notation
Before this point

The parameter A is used to represent open-loop
gain of an op amp.
The parameter G is used to represent ideal / non-
ideal closed-loop gain of an op amp.
After this point
The parameter A is used to represent ideal gain
of an op amp in a given closed-loop configuration.
The parameter G is not used.

(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
Q: What is one problem associated with the

difference amplifier?
A: Low input impedance.
Q: And, what does this mean practically?
A: That source impedance will have an
effect on gain.
Q: What is the solution?
A: Placement of two buffers at the input
terminals, amplifiers which transmit the
voltage level but draw minimal current.
(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
Q: However, can one get more from

these amps than simply impedance
matching?
A: Yes, maybe additional voltage gain???

(0195323033)
2.4.2. The
Instrumentatio
Figure 2.20: A popular circuit for an instrumentation
n Amplifieramplifier.
stage #1 stage #2
question: however, can we get more from these amps
non-
than simply impedance matching?
inverting op
answer: yes, maybe additional voltage gain???
amp (A1)
difference op
vOut = (1 +
amp (A3)
R2/R1)vIn
vOut =
non- (R4/R3)vdf
inverting op
amp (A )
(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
Q: However, can one get more from

these amps than simply impedance
matching?
A: Yes,
transfer maybe
function for additional voltage gain???
instrumentation amplifier of figure 2.20.
6 4 4 4 7 4 4 48
R4 R2 additional voltage
vOut 1 vdf
R3 R1 gain
1 4 2 43
AInst (R)

(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
advantages of instrumentation amp

very high input resistance
high differential gain
symmetric gain (assuming that A1 and A2 are
matched)
disadvantages of instrumentation amp
ADi and ACm are equal in first stage meaning
that the common-mode and differential inputs
are amplified with equal gain
(0195323033)
What is
problem
with ACm = A?
vIn1 vIn1 A=
10
A=
A = 10 x 25
25
vIn2 vIn2
differential gain >> common- differential gain = common-mode

mode gain gain
(0195323033)
differential
gain >>
common-mode
gain
vIn1 =
10.03V
vOut= 250 x (10.03-
A = 10 x
25
10.02)V
vOut = 2.5V no
vIn2 = problem!!!
10.02V Oxford University Publishing
(0195323033)
differential
gain =
common-mode
gain
vOut1= 10 x 10.03 = 15V
vIn1 =
saturation
10.03V
A=
A= 25 vOut= 25 x (15-15)V
10
vOut = 0V problem!!!
vIn2 = vOut2= 10 x 10.02 = 15V

10.02V Oxford University Publishing saturation
(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
advantages of instrumentation amp

very high input resistance
high differential gain
symmetric gain (assuming that A1 and A2 are matched)
disadvantages of instrumentation amp
ADi and ACm are equal in first stage meaning that the
common-mode and differential inputs are amplified with
equal gain
need for matching if two op amps which comprise
stage #1 are not perfectly matched, one will see
unintended effects

(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
Q: How can one fix this (alleviate these

disadvantages)?
A: Disconnect the two resistors (R1)
connected to node X from ground,
making the configuration floating in
nature
A: Refer to following slide

(0195323033)
2.4.2.
Figure 2.20: The circuit for an instrumentation
A popular
amplifier. (b) The circuit in (a) with the connection
Instrumentation
between node X and ground removed and the two
Amplifier
resistors R1 and R1 lumped together. This simple wiring
change dramatically improves performance.

(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
Q: How can one analyze this circuit?

(0195323033)
2.4.2. The for both op amp A1 and A2
6 47 48
Instrumentati v( ) v() 0
on Amplifier ...therefore
v() v()
step #1: note that
virtual short circuit
exists across terminals 64 v7InDi48
of op amp A1 and A2 vIn2 vIn1
iR1
step #2: define 2R1
current flow across the
resistor 2R1 because no current will flow
into ideal op amp, all of iR1 will
step #3: define flow across R2
6 4 47 4 48
output of A1 and A2 vOut1 vIn1 iR1R2
vOut2 vIn2 iR1R2
(0195323033)
2.4.2. The
Instrumentatio
n Amplifier
short-
vOut1
ckt
iR1
vOut2

(0195323033)
2.4.2. The
Instrumentati action: define (from equations above) the
differential input vOut 2 vOut 1 to stage #2
64444444744444448
on Amplifier v v
vOut2 vOut1 vIn2 In2 In1 R2 K
1 4 4 4 22R41 4 4 3
step #4: Define vOut 2 vIn2 iR1R2
vIn2 vIn1
output of A1 and K vIn1 R2
A2 in terms of 1 4 4 4 22R 41 4 4 3
vOut 1vIn1iR1R2
input alone 6 4 4 4 4 4action 44 7 4 4 4 4 4 4 48
: combine terms
64 v7InDi48
vIn2 vIn1
vOut2 vOut1 (vIn2 vIn1) 2 R2
14 2 43 2R1
vInDi

2R
vOut2 vOut1 1 2 vInDi
2R1
(0195323033)
2.4.2. The
Instrumentati
on Amplifier action: define in
terms of vdf
R4 6 4 7 4 8
step #5: Define vOut (vOut2 vOut1)
R3
output of A3.
step #6: Define gain R4 2R2
vOut 1 vdf
of revised R3 2R1
instrumentation
amplifier.
vOut R4 2R2
ADi 1
vdf R3 2R1
solution
(0195323033)
Instrumentation
Amplifier
6
4
5 8
3
9

98
EXAMPLE 2.3
Design The instrumentation amplifier circuit to provide a gain that can
be varied over the range of 2 to 1000 utilizing a 100 k variable
resistance ( a potentiometer or pot for short).
(Sol
.)
R4 R2
Ad 1 (2.21)
R3 R1
- It is usually preferable to obtain all the required
gain in the first stage. (Low Noise)
- The second stage (difference amp) is usually
designed for a gain of 1.
- We select all the second-stage resistors to be 10 2 R2
1 2 to 1000
k, practically convenient value. R1 f R1
R
A d 1 2 2 R2
R1 1 1000
R1 f
2 R2
1 2
R1 f 100 k
R1f =100.2 , R1f =100 ,
1%
R2 = 50.050 k, R2 = 49.9 k,
1%
99
2.5 Effect of Finite Open-Loop Gain and Bandwidth on
A circuit designer has to be thoroughly familiar with the
Circuit characteristics of practical op
Performance
amps and the effects of such characteristics on the performance of op-amp circuits.
2.5.1 Frequency Dependence of the Open-Loop Gain
- Internally compensated op amps are units that

have a network (usually a single capacitor)
- within the ICfunction
Capacitors chip. is to cause the op-amp
gain to have the STC low-pass response.
- This process of modifying the open-loop gain is
termed as frequency compensation.
- The purpose of frequency compensation is to
ensure that the op-amp will be stable (as
oppose to oscillation: Ch. 8).
A0
A( s ) (2.24)
1 s / b
Figure 2.22 Open-loop gain of a typical A0
general-purpose internally A( j ) (2.25)
compensated op amp. 1 j / b
A 0 b A 0b
? b , A(j ) ; (2.26) A(j ) = (2.27)
j
When A 1, t A 0 b (2.28) - ft = t/2 is specified on the data sheet as unity-
t t f gain band width.
? b , A(s ) ; (2.30) A(j ) ; = t (2.31)
s f
100
t f
A(j ) ; = t (2.31)
f
- If ft is known, one can easily determine the magnitude of the op-amp gain at a given
The production spread in the value of ft frequency when f >> fb.
ft is preferred as a
between op-amp units of the same type
specification parameter.
(part number) is much smaller than that
of A0 and fb.
- An op amp having this -6 dB/octave (= - 20 dB/decade) gain roll off is said to have
a single-pole model.
A0
A( s ) (2.24) pole: s=- b
1 s / b
- Since this single pole dominates the amplifier frequency response, it is called a
(for more on poles and zeros, refer to dominant pole.
Appendix E.)
2.5.2 Frequency Dependence of the Closed-Loop Gain
The effect of limited op-amp gain and bandwidth on the closed-loop
transfer functions.
Vo R2 / R1
We know
Vi 1 (1 R2 / R1 ) / A
A0
and A( s ) (2.24)
1 s / b
Vo ( s ) R2 / R1
Then, (2.33)
Vi ( s ) 1 R s
1 1 2
A0 R1 t /(1 R2 / R1 )
101
R2 Vo ( s ) R2 / R1
for A0 ? 1 , ; (2.34) Low-Pass STC Network !
R1 Vi ( s ) s
1 t
t /(1 R2 / R1 ) corner frequency, 3dB (2.35)
1+R2 / R1
Vo 1 R2 / R1
We know, (2.36)
Vi 1 (1 R2 / R1 ) / A
Vo ( s ) 1 R2 / R1
Similary, ; (2.37)
Vi ( s ) s
1
t /(1 R2 / R1 )
EXAMPLE 2.4
ft = 1 MHz, find 3-dB frequency of closed-loop
amp with gain of 1000, 100, 10, 1, -1, -10, -100, R1
-1000
R1 R2
Gain-bandwidth product = 1000 V/V-

kHz
Microelectronic Circuits - Fifth Edition Sedra/Smith Non-inverting
= 60dB-kHz amplifier 102
2.6 Large-signal Operation of Op Amps
2.6.1 Output Voltage Saturation
Rated output voltage (output saturation

voltage)
= L (L=VDD V )
2.6.2 Output Current Limits
For example, maximum output current of 741 is

20 mA.
EXAMPLE 2.5
Output saturation voltage = 13 V, output current

(a) Output voltage for limits
V =1 = V,
R 20
p= 1mA
k L
o/ I = (1+R2/R1): Vop = 10 V, Iop = 10 mA

(b) Output voltage for Vp =1.5 V, RL= 1 k
Vop = 15 V, Iop = 14.3 mA
(c) for RL= 1 k, Vpmax = ? for undistorted output.
13/10 = 1.3 V ( 14.3 mA)
(d) for Vp =1.5 V, RLmin = ? for undistorted output.
10 V 10 V
iO max 20 mA
RL min 9 k + 1 k

RL min 526
103
2.6.3 Slew Rate - Another nonlinear distortion due to the large
output signal d O
Slew Rate : maximum rate of change possible at the output SR = (V/s) (2.38)
of a real op amp dt max
Why this happens ? :

SR isChap. 9 from the finite op-amp bandwidth.
distinct
- The limited bandwidth : linear, no distortion, but reduced gain at
higher
- The limited Slew-rate : nonlinear distortion, even frequency.
at low frequency when
output is too large.
When V is sufficiently small, the
output can be the exponentially
rising ramp.
d ( A sin t ) Vo ( s ) 1 R2 / R1
= A cos t ; (2.37)
dt Vi ( s ) s
1
t /(1 R2 / R1 )
VO 1
When R1 , R2 0, (2.39)
Vi 1 s / t
This is a low-pass STC response.
Output from capacitor of RC
Microelectronic Circuits - Fifth Edition t ) V (1 e t ) (2.40) network !
O (Sedra/Smith t
104
2.6.4 Full-Power Bandwidth

I V i sin t ,
If SR < V i ,
d I
V i cos t
dt
SR Figure 2.27 Effect of slew-rate

MVo max SR fM (2.41) full-power bandwidth limiting on output sinusoidal
2 Vo max waveforms.
At which an output sinusoid with amplitude equal to the rated output

voltage of the op amp begins to show distortion due to slew-rate limiting.
M
Vo Vo max (2.42) Maximum amplitude of the undistorted output sinusoid.

2.7 DC Imperfection
2.7.1 Offset Voltage
Op amps are direct-coupled They are prone to dc
devices. problems.
With inputs being zero, the
amplifier output rests at some dc
voltage level instead of zero. The
equivalent dc input offset
voltage is
V
V o 10 mV(0.25 mV w/high cost)
OSMicroelectronic
A Circuits - Fifth Edition Sedra/Smith
105
R1 =1.2 k, R2 = 1 M,
To include effect of offset
voltage, V 3 mV
OS
o A ic V

id CMRR OS O = ?

1 M
If id =0, V 1 (0.003) 2.5V
O 1.2k

ic
o A VOS A( ) When an input signal is applied to the
CMRR
OS amplifier, the corresponding signal

output will be superimposed on the 2.5 V
ic Then the allowable signal swing at dc.
the
CMRR V/V output will be reduced.
V
OS If signal is dc, we would not know where
(another interpretation of the output is due to VOS or the signal.
CMMR)
Thus, CMRR is a measure of how * To overcome dc offset problem
total offset voltage vOS changes from
its dc value VOS when common-mode
voltage is applied.
* The gain will fall off at

the low- frequency.
Figure 2.28 Circuit model for an op amp with input

offsetSedra/Smith
Microelectronic Circuits - Fifth Edition voltage VOS.
106
2.7.2 Input Bias and Offset Current
* To find the dc output voltage of the
In order for the op amp to operate, its closed-loop amp due to the input bias
two input terminals have to be current
supplied with current, Why?
termed the
input bias current.
Bias currents ( base currents in BJTs or
gate currents in MOSFETs or JFETs) are
similar in value with directions
depending on internal amplifier circuit
type.
VO I B1 R2 ; I B R2 (2.44)
How to reduce the dc output voltage due
to the input bias current
I B1 I B 2
IB : input bias current in data sheet
2
I OS I B1 I B 2 : input offset current
VO I B 2 R3 R2 ( I B1 I B 2 R3 / R1 ) (2.45)
if I B 1 I B 2 I B , VO I B R2 R3 (1 R2 / R1 )
R2 RR With this R 3 and I B1 I B 2 ,
For minimum VO , R3 1 2 (2.46)
1 R
Microelectronic Circuits R1 Sedra/Smith
2 / REdition
- Fifth 1 R2 VO I OS R2 < I B R2 (2.47)
107
Conclusion: To minimize the effect of the input
bias current,
Place in the positive lead a

resistance equal to the dc
resistance seen by the inverting
terminal.
There should be a continuous dc path between each input terminal and ground.
This circuit will not This circuit will work.

work.

108
2.5.
Integrators
and
Differentiators
integrator / differentiator amplifier is
one which outputs an integral or derivative
of the input signal.

(0195323033)
2.5.1. The Inverting
Configuration
with General
Impedances
Q: Does the transfer function for the inverting

op amp change if the feedback and input
impedances are not purely resistive?
A: No, not in form

(0195323033)
Example 2.4:
Other Op-Amp
Configurations
Consider the circuit on next slide page.

Q(a): Derive an expression for the transfer
function vOut / vIn.
Q(b): Show that the transfer function is of a
low-pass STC (Single Time constant) circuit.
Q(c): By expressing the transfer function in
standard form of Table 1.2, find the dc-gain
and 3dB frequency.

(0195323033)
Example 2.4:
Other Op-Amp
Configurations
Figure 2.23: Circuit for

Example 2.4.
(0195323033)
2.5.2. The
Inverting
Integrator
Q: How can inverting op-amp be adapted to

perform integration?
A: Utilization of capacitor as feedback
impedance.

(0195323033)
2.5.2. The
Figure 2.24: (a) The miller or inverting integrator.
Inverting
(b) Frequency response of the integrator.
Integrator
initial
output
voltage
1
t
678
transient description (dc): .vOut (t)
RC
1 F
t0vIn(t)dt vOut (t0)
vOut 1
steady-state description (ac):
vIn sRC
1 F
(0195323033)
2.5.2. The
Inverting
Integrator
Q: What is the problem with this configuration

(related to dc gain)?
A: At dc frequency (= 0), gain is infinite
Gain = 1 / (R1CF)
Q: Solution?
A: By placing a very large resistor in parallel
with the capacitor, negative feedback is
employed to make dc gain finite.

(0195323033)
Figure 2.25: The Miller integrator with a large
2.5.2. The Inverting
resistanceIntegrator
RF connected in parallel with C in order to
provide negative feedback and hence finite gain at dc.
transient description (dc): depends on input signal???

vOut RF / R1
steady-state description (ac):
vIn 1 sRFCF
(0195323033)
Example 2.5:
Miller Integrator
Consider the Miller integrator

Q(a): Find response of a Miller Integrator to
input pulse of 1V height and 1ms width.
R1 = 10kOhm, CF = 10nF
Q(b): If the integrator capacitor is shunted by
a 1MOhm resistor, how will the response be
modified?
note: the op amp will saturate at +/- 13V
(0195323033)
2.5.3. The Op-
Amp
Differentiator
Q: How can one adapt integrator to perform

differentiation?
A: Interchange locations of resistors and
capacitors.
Oxford University PublishingFigure 2.27: A

(0195323033)
2.5.3. The Op-
Amp
Differentiator
dvIn(t)
transient description (dc): vOut (t) RFC1
dt
VOut (s)
steady-state description (ac): sRFC1
VIn(s)
Oxford University PublishingFigure 2.27: A

(0195323033)
2.5.3. The Op-
Amp
Differentiator
filtering characteristic is high pass filter

magnitude of transfer function is |VOut / VIn| = RFC1
phase of transfer function is = -90O
differentiator time-constant is frequency at which
unity gain occurs and defined as = 1 / RFC1
Q: What is the problem with differentiator?
A: Differentiator acts as noise amplifier, exhibiting
large changes in output from small (but fast)
changes in input. As such, it is rarely used in
practice.
(0195323033)
2.6. DC
Imperfections
Q: What will be discussed moving on?

A: When can one NOT consider an op amp
to be ideal, and what effect will that have
on operation?

(0195323033)
2.6.1. Offset
Voltage
Q: What is input
offset voltage (VOS)?
A: An imaginary
voltage source in
series with the
user-supplied input,
which effects an op
amp output even
when idf = 0. Figure 2.28: circuit
What will happen when model for an op amp with
short is applied?
Oxford University Publishing input offset voltage VOS.
(0195323033)
2.6.1. Offset
Voltage
Q: What causes VOS?

A: Unavoidable
mismatches in the offset dc offset
output voltage
differential stage of the } } RF
op amp. It is impossible VdcOut VOS 1
R1
to perfectly match all
transistors.
Q: Range of magnitude?
A: 1mV to 5mV
(0195323033)
This relationship between offset voltage (VOS) and
2.6.1. Offset
offset dc output (VOsOut) applies to both inverting and
Voltage
non-inverting op amp. However, only if one assumes
that VOS is present at non-inverting input.
Q: What causes VOS?

A: Unavoidable
mismatches in the offset dc offset
output voltage
differential stage of the } } RF
op amp. It is impossible VdcOut VOS 1
R1
to perfectly match all
transistors.
Q: Range of magnitude?
A: 1mV to 5mV
(0195323033)
2.6.1. Offset
Voltage
Q: How can this offset be reduced?

A: offset nulling terminals A variable
resistor (if properly set) may be used to
reduce the asymmetry present and, in turn,
reduce offset.
A: capacitive coupling A series
capacitor placed between the source and
op amp may be used to reduce offset,
although it will also filter out dc signals.

(0195323033)
Figure 2.30: The output dc offset voltage of an op-
amp can be trimmed to zero by connecting a
potentiometer to the two offset-nulling
terminals. The wiper of the potentiometer is
connected to the negative supply of the op amp.

(0195323033)
Figure 2.31: (a) A capacitively-coupled
inverting amplifier. (b) The equivalent circuit for
determining its dc output offset voltage VO.
dc signals cannot
pass!

(0195323033)
2.6.2. Input
Bias Figure 2.32: The op-
and Offset amp input bias currents
represented by two
Currents
current sources IB1 and IB2.
input bias current -
is the dc current which
must be supplied to
the op-amp inputs for
proper operation.
Ideally, this
current is zero
input offset current
- the difference
between bias current
at both terminals
(0195323033)
2.6.2: Input
Bias Figure 2.32: The op-
bias current
and Offset amp input atbias currents
terminals
#1 and #2two
Currents 678
represented by
current sources IB1 and IB2.
IB1 IB2
input
input bias
bias current:
current - is . IB
the dc current which 2
must be supplied to the difference
op-amp inputs for between bias'
proper operation. 64 7 48
input offset
Ideally, current:
this current IOS IB1 IB2
is zero
input offset current -
the difference between
bias current at both 6 4 7 48
resulting output voltage:
terminals VBOut IB1RF
(0195323033)
2.6.2. Input
Bias
and Offset
Currents
Q: How can this bias resistor placed between
non-inverting input
be reduced? and ground (R3) should
equal parallel connection
A: Placement of R3 of inverting input
resistance and feedback
as additional resistor 6 47 48
between non- RR
inverting input and R3 1 F
ground. R1 RF
Q: How is R3 defined?
A: Parallel
connection of RF and
R1.
(0195323033)
2.7.1. Frequency
Dependence
of the Open-Loop
Gain
The differential open-

loop gain of an op-
amp is not infinite.
It is finite and
decreases with
frequency.
It is high at dc, but
falls off quickly
starting from 10Hz. Figure 2.39: Open-loop
gain of a typical general-
purpose internally
(0195323033)
compensated op amp.
2.7.1. Frequency
Dependence
of the Open-Loop
Gain
internal compensation
is the presence of internal
passive components (caps)
which cause op-amp to
demonstrate STC low-pass
response.
frequency compensation
Figure 2.39:
is the process of modifying
Open-loop gain of a
the open-loop gain. typical general-
The goal is to increase purpose internally
stability Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith compensated op
(0195323033)
2.7.1: Frequency
The Dependence
gain of an internally compensated op-
amp mayOpen-Loop
of the be expressed as shown below
Gain
A0
transfer function in Laplace domain: A(s)
1 s/ b
A0
transfer function in frequency domain: A(j)
1 j / b
A0b
transfer function for high frequencies: A(j)
1 44 2 4 j43
b is break frequency
A0b t
magnitude gain for high frequencies: A(j)
j
unity gain occurs at t :
t A0b
(0195323033)
2.7.2. Frequency
Response of
Closed-Loop VOut R2 / R1

Amplifiers VIn 1 (1 R2 / R1)/ ({A)
open
loop
gain
Q: How can we create a VOut R2 / R1 R2 / R1

VIn 1 1 R2 / R1 1 R2 / R1
more accurate description
1 (1 s/ b)
A0 A
1 4 40 4 2 4 4 4 3
of closed loop gain for an
114 2s/43
0 action: split these terms
inverting-type op-amp? A from two
slides back
step #1: Define closed-
VOut R2 / R1
loop gain of an inverting
VIn 1 R2 / R1 s 1 R2 / R1
amplifier with finite open- 1
A
1 4 204 3 A
loop gain (A) 1 b4 4 2 40 43
action: replace with 0 action: replace with...
because A0 1R2 / R1
step #2: Insert
frequency-dependent VOut R2 / R1

description of A from last VIn s 1 R2 / R1
1
t
slide
solution
step #3: Assume A0 >>
1 + R2/Rby
Microelectronic Circuits
1Adel S. Sedra and Kenneth C. Smith
(0195323033)
2.7.2. Frequency
Response of
Closed-Loop
Amplifiers
Q: How can we create a more accurate

description of closed loop gain for an both
inverting and non-inverting type op-amps?
6 4 4inverting
44 7 op4amp
4 4 48 644 non-inverting op amp
44 7 4 4 4 48
VOut R2 / R1 VOut 1 R2 / R1

VIn s 1 R2 / R1 VIn s 1 R2 / R1
1 1
t t

(0195323033)
2.7.2. Frequency
Response of
Closed-Loop
Amplifiers
3dB frequency is
the frequency at
which the amplifier t
3dB
gain is attenuated 1 R2 / R1
3dB from maximum
(aka. dc ) value.

(0195323033)
2.8. Large-
Signal
Operation of
Op-Amps
2.8.1. Output 2.8.2. Output
Voltage Saturation Current Limits
If supply is +/- iOut current of op-
15V, then vOut will amp, including that
saturate around which facilitates
+/- 13V. feedback, cannot
exceed X.
The book
approximates X at
20mA.
(0195323033)
2.8.3. Slew
Rate
slew rate is
maximum rate of
change of an op-amp slew rate (SR)
(V/us) 6 44 7 4 48
dvOut
Q: How can this be SR
dt max
problematic?
A: If slew rate is
less than rate of
change of input.
(0195323033)
2.8.3. Slew
Rate
Q: Why does slewing

occur?
A: In short, the
bandwidth of the
op- amp is limited
so the output at
very high
frequencies is
attenuated
(0195323033)
2.8.4. Full-
Power
Bandwidth
Op-amp slewing will vIn VIn sin t

cause nonlinear
distortion of
dvIn
sinusoidal VIn cos t
waveforms dt
sine wave
rate of change

(0195323033)
2.8.4. Full-
Power
Bandwidth
rated
full-power bandwidth (fM) the output
FP voltage
band. A*vIn
maximum frequency at which } 678
SR M VOutMax
amplitude of a sinusoidal input and
output are equal SR
maximum output voltage (VOutMax) fM
2 V
1 44 2 4OutMax
43
is equal to (A*vIn) full-power bandwidth
note: an inverse relationship exists

between fM and VOutMax
this value
cannot be
greater
note: beyond M, output may be

than one
}

defined in terms of VOut VOutMax M
1 4 44 2 4 4 43
relationship between
Oxford University Publishing actual output and maximum
(0195323033)
Conclusion
The IC op-amp is a versatile circuit building

block. It is easy to apply, and the
performance of op-amp circuits closely
matches theoretical predictions.
The op-amp terminals are the inverting
terminal (1), the non-inverting input terminal
(2), the output terminal (3), the positive-
supply terminal (4) to be connected to the
positive power supply (VCC), and the negative-
supply terminal (5) to be connected to the
negative supply (-V ).

(0195323033)
Conclusion (2)
The ideal op-amp responds only to the

difference input signal, that is (v2 - v1). It
yields an output between terminals 3 and
ground of A(v2 - v1). The open-loop gain (A) is
assumed to be infinite. The input resistance
(Rin) is infinite. The output resistance (Rout) is
assumed to be zero.
Negative feedback is applied to an op-amp by
connecting a passive component between its
output terminal and its inverting (aka.
(0195323033)
Conclusion (3)
Negative feedback causes the voltage

between the two input terminals to become
very small, and ideally zero. Correspondingly,
a virtual short is said to exist between the
two input terminals. If the positive input
terminal is connected to ground, a virtual
ground appears on the negative terminal.

(0195323033)
Conclusion (4)
The two most important assumptions in the

analysis of op-amp circuits, assuming
negative feedback exists, are:
the two input terminals of the op-amp are
at the same voltage potential.
zero current flows into the op-amp input
terminals.
With negative feedback applied and the loop
closed, the gain is almost entirely determined
by external components: Vo/Vi = -R2/R1 or
(0195323033)
Conclusion (5)
The non-inverting closed-loop

configuration features a very
high input resistance. A special
case is the unity-gain follower,
frequently employed as a buffer
amplifier to connect a high-
resistance source to a low-
Figure 2.16
resistance load.
The difference amplifier of Figure
2.16 is designed with R4/R3 =
R2/R1, resulting in vo = (R2/R1)(vI2
(0195323033)
Conclusion (6)
The instrumentation amplifier

of Figure 2.20(b) is a very
popular circuit. It provides vo =
(1+R2/R1)(R4/R3)(vI2 - vI1). It is
usually designed with R3 = R4
and R1 and R2 selected to
provide the required gain. If an Figure
2.20(b)
adjustable gain is needed, part
of R1 can be made variable.
(0195323033)
Conclusion (7)
The inverting Miller Amplifier of Figure

2.24 is a popular circuit, frequently
employed in analog signal-processing
functions such as filters (Chapter 16)
and oscillators (Chapter 17).
The input offset voltage (VOS) is the
magnitude of dc voltage that when
applied between the op-amp input Figure 2.24
terminals, with appropriate polarity,
reduces the dc offset at the output.

(0195323033)

Chapter 2 Op Amp

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Chapter 2 Op Amp

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Course Outline

Oxford University Publishing

IN THIS CHAPTER YOU WILL LEARN

Oxford University Publishing

IN THIS CHAPTER YOU WILL LEARN

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You have studied and understood (Hopefully)

Gain......Voltage, Current, Inverting, non-inverting

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Usually Called Op Amps

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ideal input characteristic is infinite impedance

Q: But, is an amplifier with infinite gain of

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Q: How is common-mode input (vcmi)

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Parameter Variable Typical Ideal

Open loop gain (AoL ): Usually several thousand.

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Note that the inverting input and non-inverting

The internal circuitry in the op amp tries to force the

When Vs is equal to 0V, Vo = 0V.

Given how an op amp functions, what do you expect

Given how an Op Amp functions and A= 103, what do

Q: What are two basic closed-loop op-amp

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Q: How does one analyze closed-

virtual ground exists at v1

step #3: Define current in to inverting input

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step #5: Define vOut virtual

note: this expression is one of the

question: how will we

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Q: How does the gain expression change if

Microelectronic Circuits - Fifth Edition Sedra/Smith

Q: Under what condition can G = -R2 / R1

ideal gain Oxford University Publishing

Problem Statement: Consider an inverting

(a ) R1 1 k, R2 100 k, A=10 3 ,10 4 ,10 5 , % error of G to ideal G= ?

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Q: What is input resistance for inverting op-amp?

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The output voltage in summing amplifier is

vo=-if*Rf since vi=0

The output voltage in summing amplifier is

vo=-if*Rf since vi=0

if=iA+iB=vA/RA+vB/RB => vo=-(vA/RA+vB/RB)*Rf

Find the currents and voltages in these two circuits:

i2=i1=1mA from KCL

Find the currents and voltages in these two circuits:

vo=- i2*1k- i4*1k=-10 V

Find expression for the output voltage in the amplifier circuit:

Find expression for the output voltage in the amplifier circuit:

vo =- i5*R5=-(v3/10k +v2/10k )*20k =-2v3 -2v2 =4v1 -2v2

When we flip the polarization of the op-amp as shown on the

non-inverting op-amp configuration

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vo=- i21k- i41k=-10 V

vo =- i5R5=-(v3/10k +v2/10k )20k =-2v3 -2v2 =4v1 -2v2