Combinational

Circuit Design
 Outline
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates

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Combinational Circuits
 Example 1
module mux(input s, d0, d1,
output y);

assign y = s ? d1 : d0;
endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0
S
Y
D1
S

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Combinational Circuits
 Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.

D0
S
Y
D1
S

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Combinational Circuits
 Bubble Pushing
Start with network of AND / OR gates
Convert to NAND / NOR + inverters
Push bubbles around to simplify logic
Remember DeMorgans Law

Y Y

(a) (b)

Y Y

D
(c) (d)

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Combinational Circuits
 Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.

D0
S
Y
D1
S

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Combinational Circuits
 Compound Gates
Logical Effort of compound gates

Y=AB+C Y=AB+CD Y=A(B+C)+DE

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Combinational Circuits
 Example 4
The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the two designs.
H = 160 / 16 = 10 B = 1 N = 2
D0 D0
S S
Y Y
D1
D1
S S
P 224 P 4 1 5
G (4 / 3)g(4 / 3) 16 / 9 G (6 / 3)g(1) 2
F GBH 160 / 9 F GBH 20
f N F 4.2 f N F 4.5
D Nf P 12.4 D Nf P 14

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Combinational Circuits
 Input Order
Our parasitic delay model was too simple
Calculate parasitic delay for Y falling
If A=1 arrives latest? 6RC=2Since 3RC
If B=1 arrives latest? By Elmore delay
(2C)( R) +(6C)( R + R) =7RC=2.33

2 2 Y
A 2 6C

B 2x 2C

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Combinational Circuits
 Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance)
Boost size of noncritical input A
Y
reset
So total resistance is same
gA = 10/9 2 2
Y
gB = 2 A 4/3
reset 4
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
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Combinational Circuits
 Symmetric Gates
Inputs can be made perfectly symmetric

2 2
Y
A 1 1
B 1 1

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Combinational Circuits
 Skewed Gates
Skewed gates favor one edge over another
Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
HI-skew unskewed inverter unskewed inverter
inverter (equal rise resistance) (equal fall resistance)

2 2 1
A Y A Y A Y
1/2 1 1/2

Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that edge.
gu = 2.5 / 3 = 5/6
gd = 2.5 / 1.5 = 5/3
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Combinational Circuits
 HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.

Skewed gates reduce size of noncritical transistors

HI-skew gates favor rising output (small nMOS)
LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
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Combinational Circuits
Catalog of Skewed Gates
Inverter NAND2 NOR2

2 2 B 4
Y
2 A 4
A 2
unskewed A Y Y
1 gu = 1 B 2 gu = 4/3 1 1 gu = 5/3
gd = 1 gd = 4/3 gd = 5/3
gavg = 1 gavg = 4/3 gavg = 5/3

2 2 B 4
Y
2 A 4
A 1
HI-skew A Y Y
1/2 g = 5/6 B 1 gu = 1 1/2 1/2 gu = 3/2
u
gd = 5/3 gd = 2 gd = 3
gavg = 5/4 gavg = 3/2 gavg = 9/4
1 1 B 2
Y
1 A 2
A 2
LO-skew A Y Y
1 gu = 4/3 B 2 gu = 2 1 1 gu = 2
gd = 2/3 gd = 1 gd = 1
gavg = 1 gavg = 3/2 gavg = 3/2

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Combinational Circuits
 Asymmetric Skew
Combine asymmetric and skewed gates
Downsize noncritical transistor on unimportant
input
Reduces parasitic delay for critical input

A
Y
reset

1 2
Y
A 4/3
reset 4

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Combinational Circuits
 Observations
For speed:
NAND vs. NOR
Many simple stages vs. fewer high fan-in stages
Latest-arriving input
For area and power:
Many simple stages vs. fewer high fan-in stages

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Combinational Circuits
 Example 5
Annotate your designs with transistor sizes that
achieve this delay.

8 8
8 10 10
8 25 25 10 10 24
Y Y
25 6 6 12
8 8 25 6 6
8
8
16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36

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Combinational Circuits