Interfacing to 7-Segment Numeric

Displays
Input: 0V =OFF, or 5V = ON
= 5V

0 (GRND) Input: 0V= ON,

or 5V = OFF
http://
thelearningpit.com/lp/doc/7seg/7seg.ht
 Theory of LED dot matrix display
http://embedded-lab.com/blog/?p=2478
In a dot matrix display, multiple LEDs are wired together in rows and columns.
This is done to minimize the number of pins required to drive them.
For example, a 88 matrix of LEDs (shown below) would need 64 I/O pins, one for
each LED pixel.
By wiring all the anodes together in rows (R1 through R8), and cathodes in columns
(C1 through C8), the required number of I/O pins is reduced to 16.
Each LED is addressed by its row and column number. In the figure below, if R4 is
pulled high and C3 is pulled low, the LED in fourth row and third column will be turned
on.
Characters can be displayed by fast scanning of either rows or columns.
 Scanning across the columns and feeding with appropriate
row values
For example: to Display A , see the figures below.
http://embedded-lab.com/blog/?p=2478#sthash.56scCKmD.dpuf

PB0

PB1

PB2

PB3

PB4

PB5 PP4 PP3 PP2

PP1 PP0

1.PB6
We will first select the column C1
(which means C1 is pulled low in this
case), and deselect other columns by
blocking their ground paths (one way of
doing that is by pulling C2 through C5
2. Now, the first column is
active, and you need to turn
on the LEDs in the rows R2
through R7 of this column,
which can be done by
3. Next, select the
column C2 (and deselect
all other columns), and
apply forward bias to R1
and R5, and so on.
http://embedded-lab.com/blog/?p=2478

Row values of each column for displaying the

 Four Segments 5 x 7 Alphanumeric Displays

http://pdf1.alldatasheet.com/datasheet-pdf/view/64648/HP/HDLX-
2416.html
 M a in m e m o r y

R A M R O M FLA S H

D R A M S R A M M -R O M PR O M E PR O M E E PR O M
 STATIC RANDOM ACCESS MEMORY (SRAM)
SRAM circuitry is a "flip-flop.

It is faster than that of DRAM (The fastest SRAM may be as much as 7 times
faster than DRAM).

But it uses more power and generates more heat.

SRAM MEMORY is normally "cache" memory, known as "L2.

Cost: SRAM is, byte for byte, several times more expensive than DRAM.

SRAM is physically larger.

http://www.tpub.com/content/fc/14100/css/14100_157.htm
 Flash memory
A special type of EPROM or EEPROM that can be erased and
reprogrammed in blocks instead of one byte at a time.

Many modern PCs have their BIOS stored on a flash memory chip so that it
can easily be updated if necessary.

Such a BIOS is sometimes called a flash BIOS.

Flash memory is also popular in modems because it enables the modem

manufacturer to support new protocols as they become standardized.

http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC10.PDF
 Electrically Erasable Programmable ROM
(EEPROM)

Electrically Erasable Programmable ROM (EEPROM):

The next level of erasability is the EEPROM, which can be erased under
software control.

This is the most flexible type of ROM, and is now commonly used for
holding BIOS programs.

When you hear reference to a "flash BIOS" or doing a BIOS upgrade by

"flashing", this refers to reprogramming the BIOS EEPROM with a special
software program.

Here we are blurring the line a bit between what "read-only" really means,
but remember that this rewriting is done maybe once a year or so, compared
to real read-write memory (RAM) where rewriting is done often many times
per second!
HCS 12 Internal Architecture
 HCS12 Memory Map
Address Usage
Range
Mode Details PAD0 PAD1
$0000-$03FF Registers
$0400-$0FFF EEPROM 1 EVB mode 0 0

$1000-$1FFF RAM (User Data) Jump-to-EEPROM

2 0 1
mode
$2000-$3FFF RAM (User Program)
3 POD mode 1 0
$4000-$7FFF 16K fixed Flash
BOOTLOADER
$8000-$BFFF 16K page window 4
mode
1 1

$C000-$FFFF 16K fixed Flash

 Project >>Options >>
Change from RAM to EEPROM Mode