Lecture Note 1

MOS Field-Effect Transistors (MOSFETs)
INTRODUCTION
Having studied the junction diode, which is the most basic two-
terminal semiconductor device, we now turn our attention to three-
terminal semiconductor devices. Three-terminal devices are far more
useful than two-terminal ones because they can be used in a
multitude of applications, ranging from signal amplification to
digital logic and memory.
The basic principle involved is the use of the voltage between two
terminals to control the current flowing in the third terminal. In this
way a three-terminal device can be used to realize a controlled
source, which is the basis for amplifier design.
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1.1. Device structure and physical operation
1.1.1. Device structure
- The transistor is fabricated on a p-type substrate, which provides physical support for the device. Two
heavily doped n-type regions (n+ source and n- drain) are created in the substrate. A thin layer of SiO2 (an
excellent electrical insulator) is grown on the face of the substrate, covering the area between the two n-type
regions.
- Metal is deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts are also
made to the source region, the drain region, and the substrate => 4 terminals are brought out: the gate terminal
(G), the source terminal (S), the drain terminal (D) and the body terminal (B).
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 m, W = 0.2 to
100 m, and the thickness of the oxide layer (t ox) is in the range of 2 to 50 nm.
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1.1.2. Operation with Zero Gate Voltage
With zero voltage applied to the gate, two back-to-back diodes exist in series between drain and source.
One diode is formed by the pn junction between the n+ drain region and the p-type substrate, and the
other diode is formed by the pn junction between the p-type substrate and the n+ source region. These
back-to-back diodes prevent current conduction from drain to source when a voltage v GS is applied. In
fact, the path between drain and source has a very high resistance (of the order of 10 12 )
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1.1.3. Creating a Channel for Current Flow
Here we have grounded the source and the drain and applied a positive voltage to the gate. Since the source is
grounded, the gate voltage appears in effect between gate and source and thus is denoted v GS. The positive
voltage on the gate causes, in the first instance, the free holes (which are positively charged) to be repelled from
the region of the substrate under the gate (the channel region). These holes are pushed downward into the
substrate, leaving behind a carrier-depletion region.
As well, the positive gate voltage attracts electrons from
the n+ source and drain regions (where they are in
abundance) into the channel region. When a sufficient
number of electrons accumulate near the surface of the
substrate under the gate, an n region is in effect created,
connecting the source and drain regions, as indicated in
Fig. 4.2.
Figure 4.2 The enhancement-type NMOS transistor with

a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
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The value of vGS at which a sufficient number of mobile electrons accumulate in the channel region to
form a conducting channel is called the threshold voltage and is denoted Vt (0.3-1V).
- Parallel plate-capacitor between gate and the
channel region.
- The silicon dioxide is the capacitor dieletric
- The electric field developes in vertical
direction. This field controls the amount of
charge in the channel => determines the
channel conductivity => field-effect transistor
The voltage across this parallel-plate capacitor
must exceed Vt to form channel.
The effective voltage vOV (excess of vGS over Vt)
vOV = vGS - Vt
Figure 4.2 The enhancement-type NMOS transistor with a positive

voltage applied to the gate. An n channel is induced at the top of the
substrate beneath the gate.
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Figure 4.2 The enhancement-type NMOS transistor with a positive voltage

applied to the gate. An n channel is induced at the top of the substrate
beneath the gate.
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1.2. Applying a Small vDS
Having induced a channel, we now apply a positive voltage v DS between drain
and source. Consider the case where vDS is small (0.5V or so)
vDS cause the iD (the direction is from D to S).
Because vDS is small, we can assume that the voltage along the channel
remains approximately constant and equal to v GS => the effective voltage
remains equal to vOV
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS.
Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS. Note that the depletion region is
not shown (for simplicity).
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied.
The device acts as a resistance whose value is determined by vGS.
Specifically, the channel conductance is proportional to vGS Vt and thus iD
is proportional to (vGS Vt) vDS. Note that the depletion region is not shown
(for simplicity).
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4.4. Applying a Small vDS
The operation of the MOSFET as a voltage-controlled resistance is further
illustrated in Figure 4.4
Figure 4.4 The iDvDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS,
is kept small. The device operates as a linear resistor whose value is controlled by vGS.
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4.5. Operation as vDS is increased
Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its
resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
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Figure 4.5b a) Voltage across the channel. b) While the depth of the channel at the source end is still proportional to V OV, that at the drain end is
proporational to (VOV vDS)
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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated
with vGS > Vt.
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Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS Vt the channel is
pinched off at the drain end. Increasing vDS above vGS Vt has little effect (theoretically, no effect) on the channels shape.
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In the triode region:
Or:
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4.6. Operation for vDS VOV is increased
In the saturation region:
Or:
Figure 4.6b a) Operation of MOSFET with vGS Vt + VOV as vDS is increased to VOV At the drain end, vGD decreases to Vt and the channel depth at
the drain end reduces to zero (pinch off). At this point, the MOSFET enters the saturation mode of operation.
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Example 4.21
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Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well.
Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the
p-type body and to the n well; the latter functions as the body terminal for the p-channel device.
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4.2.1. The circuit symbol
Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal
to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected
to the body or when the effect of the body on device operation is unimportant.
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4.2.2. The iD vDS characteristic
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4.2.2. The iD vDS characteristic
Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of
current flow indicated. (b) The iDvDS characteristics for a device with kn (W/L) = 1.0 mA/V2.
Microelectronic Circuits - Fifth Edition
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4.2.3 The iDvGS characteristic
Figure 4.12 The iDvGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, kn W/L = 1.0 mA/V2).
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Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode
region and in the saturation region.

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4.2.3 Finite Output Resistance in Saturation
In saturation, iD is independent of vDS. Thus, a change vDS in the drain-to-source
voltage causes a zero change in iD, which implies that the incremental resistance
looking into the drain of a saturated MOSFET is infinite. That is, once the channel
is pinched off at the drain end, further increases in v DS have no effect on the
channels shape. But, in practice, increasing v DS beyond vOV does affect the channel
somewhat. Specifically, as vDS is increased, the channel pinch-off point is moved
slightly away from the drain, toward the source.
=> the channel length is in effect reduced, from L to L - L, a phenomenon known
as channel-length modulation.
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4.2.3 Finite Output Resistance in Saturation
4.3. MOSFET Circuits at DC

Having studied the currentvoltage characteristics of MOSFETs, we
now consider circuits in which only dc voltages and currents are of
concern. Specifically, we shall present a series of design and analysis
examples of MOSFET circuits at dc.
In the following examples, to keep matters simple and thus focus
attention on the essence of MOSFET circuit operation, we will
generally neglect channel-length modulation; that is, we will assume
=0
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Exercise 5.3
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Solution
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Exercise 5.4
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Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.

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Question 1:
Describe the iD vDS characteristic of Mosfet
Figure P1
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Question 1
Figure P2
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Figure 4.24 Circuit for Example 4.6.

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Figure 4.25 Circuits for Example 4.7.

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Figure E4.16

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4.4. The Mosfet as an amplifier and as a switch
In this section we begin our study of the use of MOSFETs in the design of
amplifier circuit. The basis for this important MOSFET application is that when
operated in the saturation region the MOSFET acts as a voltage-controlled current
source: Changes in the gate-to-source voltage vGS give rise to changes in the drain
current iD give rise. Thus the saturated MOSFET can be used to implement a
transconductance amplifier. However, since we are interested in linear
ampification that is, in amplifiers whose output signal (in this case, the drain
current iD) is linearly related to their input signal (in this case, the gate-to-source
voltag vGS) we will have to find away around the highly nonlinear (square-law)
relationship of iD to vGS.
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4.4.1. Large-Signal Operation The Transfer Characteristic
Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of
the amplifier in (a).
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Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.

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Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive
signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not
allow for sufficient negative signal swing.
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Figure 4.28 Example 4.8.
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Figure 4.28 (Continued)

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Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2
represent extremes among units of the same type.
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4.5.2. Biasing by Fixing VG and connecting a Resistance in the Sourse
Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement;
(b) reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate
using a capacitor CC1; (e) practical implementation using two supplies.
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Figure 4.31 Circuit for Example 4.9.
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4.5.2. Biasing using Drain-to-Gate Feedback Resistor
VGS = VDS = VDD - IDRD
Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

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4.5.2. Biasing using Constant-Current-Source
Figure 4.33 (a) Biasing the MOSFET using a constant-current

source I. (b) Implementation of the constant-current source I
using a current mirror.

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4.5.3. The Signal Current in the Drain Terminal
Figure 4.34 Conceptual circuit

utilized to study the operation of
the MOSFET as a small-signal
amplifier.
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Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.
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Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34.

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4.5.4. Small-Signal Equivalent-Circuit Models
From a signal point of view, the FET behaves
as a voltage-controlled current source.
ro = |VA| /ID
VA = 1/
Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length
modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.
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Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can
be added between D and S in the T model of (d).
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Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative
representation of the T model.
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Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body.

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Table 4.2

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Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations.

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Figure E4.30

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Table 4.3

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Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for
small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model
implicitly utilized.
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Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent circuit with
ro neglected.
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Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the
amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.

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Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c) Small-signal
analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower.

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Table 4.4

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Table 4.4 (Continued)

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Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in
which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb neglected (to
simplify analysis).
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Figure 4.48 Determining the short-circuit current gain Io /Ii.

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Table 4.5

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Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier
in (a) delineating the three frequency bands of interest.

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Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a)
simplified at the input and the output;

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Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq;
(d) the frequency response plot, which is that of a low-pass single-time-constant circuit.

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Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.

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Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are
sufficiently separated for their effects to appear distinct.

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Figure 4.53 The CMOS inverter.

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Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b)
graphical construction to determine the operating point; (c) equivalent circuit.
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Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical
construction to determine the operating point; (c) equivalent circuit.
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Figure 4.56 The voltage transfer characteristic of the CMOS inverter.

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Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms;
(c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during
the capacitor discharge.
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Figure 4.58 The current in the CMOS inverter versus the input voltage.

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Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for
the case the substrate (B) is connected to the source (S).

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Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = 4 V and kn(W/L)
= 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iDvDS characteristics; (c) the iDvGS
characteristic in saturation.
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Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and
the saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).

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Figure 4.62 Sketches of the iDvGS characteristics for MOSFETs of enhancement and depletion types, of both polarities
(operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that for generality
somewhat different values of |Vt| are shown for n-channel and p-channel devices.
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Figure E4.51

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Figure E4.52

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Figure 4.63 Capture schematic of the CS amplifier in Example 4.14.

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Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 F and CS = 0 (i.e., CS removed).

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Figure P4.18

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Figure P4.33

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Figure P4.36

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Figure P4.38

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Figure P4.41

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Figure P4.42

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Figure P4.43

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Figure P4.44

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Figure P4.45

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Figure P4.46

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Figure P4.47

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Figure P4.48

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Figure P4.54

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Figure P4.61

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Figure P4.66

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Figure P4.74

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Figure P4.75

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Figure P4.77

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Figure P4.86

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Figure P4.87

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Figure P4.88

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Figure P4.97

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Figure P4.99

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Figure P4.101

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Figure P4.104

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Figure P4.117

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Figure P4.120

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Figure P4.121

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Figure P4.123

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MOS Field-Effect Transistors (MOSFETs)

Figure 4.2 The enhancement-type NMOS transistor with

Figure 4.2 The enhancement-type NMOS transistor with a positive

Figure 4.2 The enhancement-type NMOS transistor with a positive voltage

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4.3. MOSFET Circuits at DC

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Figure 4.31 Circuit for Example 4.9.

VGS = VDS = VDD - IDRD

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Figure 4.33 (a) Biasing the MOSFET using a constant-current

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Figure 4.34 Conceptual circuit

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