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EE174 SJSU
Tan Nguyen
OBJECTIVES
Lock Range of the PLL: The range of frequencies from fi = fmin to fi = fmax where the locked PLL
remains in the locked condition. The lock range is wider than the capture range.
If the PLL is initially locked, and if fi < fmin, or fi > fmax the PLL becomes unlocked fi fosc.
When the PLL is unlocked, the VCO oscillates at the frequency fo called the center frequency, or
the free-running frequency of the VCO.
Capture Range of the PLL: The lock can be established again if the incoming signal frequency
fi gets close enough to fo. The range of frequencies fi = fo- fc to fi = fo+ fc such that the initially
Locked Range and Capture Range of the PLL
Once the PLL is in the locked condition, it remains locked as long as the VCO output
frequency fosc can be adjusted to match the incoming signal frequency fi fmin fi fmax.
When the lock is lost, the VCO operates at the free-running frequency f o, fmin fo
fmax.
To establish the lock again, i.e. to capture the incoming signal again, the incoming signal
frequency fi must be close enough to fo fo fc fi fo+ fc . The 2fc is called the capture
range.
The capture range 2fc is an important PLL parameter because it determines whether the
locked condition can be established or not. Note that the capture range 2fc < the lock
range fmax fmin.
The capture range 2fc depends on the characteristics of the loop filter. For the simple RC
filter, a very crude, approximate implicit expression for the capture range can be found
as:
where fp is the cut-off frequency of the filter, VDD is the supply voltage, and Ko is the VCO
gain.
Phase Detector (PD)
simple phase detector is an XOR gate with logic
A
low output (V = 0V) and the logic high output (V
= VDD).
An example below shows the PLL is in the locked
condition where Vi and Vosc are two phase-shifted
periodic square-wave signals at the same
frequency fosc = fi = , and with 50% duty ratios.
The output of the phase detector is a periodic
square-wave signal V(t) at the frequency 2fi , and
with the duty ratio D that depends on the phase
difference (t) = [osc(t) - i(t)] between Vi and Vosc
D = (for XOR)
The output of the XOR phase detector can be
written as the Fourier series:
The output V(t) of the phase detector is filtered by the low-pass loop filter. The purpose of the
low-pass filter is to pass the dc and low-frequency portions of V (t) and to attenuate high-
frequency ac components at frequencies 2kfi . The simple RC filter has the transfer function:
F(s) = =
where p = and fp = is the cut-off frequency of the filter.
If fp << 2fi the output of the filter Vo is approximately equal to the
dc component V of the phase detector output.
In practice, the high-frequency components are not completely eliminated
and can be observed as high-frequency ac ripple around the dc or slowly-varying V o.
Vi Vos
c
T(s) = KDF(s)KO/s
either s 2 + 2 n s + n 2 or + 1
1 = 1/RC
= 1/(120k x3.3nF) =
2525
Example
Consider a PLL with KO = 250 krad s per V and that uses a Type I (XOR)
phase detector KD = Vcc / . The supply voltage is 5 V, and a simple RC
filter (see below) is used. For the filter R = 120 k and C = 3.3 nF.
There is no other gain in the loop.
a) Determine the transfer function H(s) = o(s) i(s) of the loop.
b) Calculate natural frequency n and damping ratio .
Synthesizer PLL
We will now add the divider 1/N to the feedback path.
This architecture is called an integer-N synthesizer.
Divider /R
Four-modulus prescalers
To extend the upper frequency range of a frequency synthesizer
but still allows the synthesis of lower frequencies. The solution is
the four-modulus prescaler. The four-modulus prescaler is a
logical extension of the dual-modulus prescaler. It offers four
different scaling factors, and two control signals are required to
select one of the four available scaling factors.
Integer-N Frequency Synthesizers with Prescalers cont.
As an example, the four-modulus prescaler can divide by factors of 100, 101, 110, and
111. By definition, it scales down by 100 when both control inputs are LOW. The internal
logic of the four-modulus prescaler is designed so that the scaling factor is increased by
1 when one of the control signals is HIGH, or increased by 10 when the other control
signal is HIGH. If both control signals are HIGH, the scaling factor is increased by 1 + 10
= 11.
There are three programmable /N counters in the system: /N1, /N2, and /N3 dividers. The
overall division ratio is given by:
Ntot = 100N1 + 10N2 + N3
In this equation N3 represents the units, N2 the tens, and N1 the hundreds of
the division ratio Ntot. Here N2 and N3 must be in the range 0 to 9, and N1 must be at least
as large as both N2 and N3 because when the content of N1 becomes 0, all /N1, /N2
and /N3 counters are reloaded to their preset values, and the cycle is repeated (N 1,min =
9). The smallest realizable division ratio is consequently:
Ntot,min = 100 x 9 = 900
For a reference frequency f1 of 10 kHz, the lowest frequency to be synthesized is
therefore: 900 x f1 = 9 MHz.
Integer-N Frequency Synthesizers Examples
Numerical Example: We wish to generate a frequency that is 1023 times the
reference frequency. The division ratio Ntot is thus 1023; hence N1 = 10, N2 = 2,
and N3 = 3 are chosen. Furthermore, we assume that the /N1 counter has just
stepped down to 0, so all three counters are now loaded to their preset values.
Both outputs of the /N2 and /N3 counters are now HIGH, a condition that causes
the four-modulus prescaler to divide initially by 111.
Solution: After N2 x 111 = 2 x 111 = 222 pulses generated by the VCO, the /N 2
counter steps down to 0. Consequently, the prescaler will divide by 101. At this
moment, the content of the /N3 counter is 3 2 = 1. After another 101 pulses
(1 x 101) have been generated by the VCO, the /N3 counter also steps down to 0.
The division ratio of the four-modulus prescaler is now 100.
The content of the /N1 counter is now 7. After another 700 pulses (7 x 100) have
been generated by the VCO, the /N1 counter also steps down to 0, and the cycle is
repeated. To step through an entire cycle, the VCO had to produce a total of
Ntot = 2 x 111 + 1 x 101 + 7 x 100 = 1023 pulses, which is exactly the
number desired.
Jitters Example
Clock Data Recovery
The first CDR design required that the same clock used to serialize the
data be sent to the receiver alongside the data. This method created
some added problems for the receiver, as it had to deal with the jitter in
the data stream and with the jitter in the clock stream, alongside the data
stream. Another issue is the amount of data links is reduced by two using
this system.
Differentiation CDR
The steps taken by the algorithm to obtain the recovered data. The first plot is
the input data, the second is the differentiated input data. We can see that the
peaks occur at the zero crossings of the input data. The third plot is the fullwave
rectified differentiated data. This data is used to create a clock, which is then
used to create the fourth plot, the regenerated data
Clock Data Recovery
To counteract the effect of the system described earlier, a method
utilizing two separate clock was developed. The transmitter serializes the
data stream using the clock A. The cdr, at the receiver, uses information
from a reference clock, clock B, located at the receiver end. To
accomplish this operation a Phase-Locked Loop (PLL) is used.
Integer-N Frequency Synthesizers with Prescalers
Dual-modulus prescalers
A counter whose division ratio can be switched from one value to another by an
external control signal. As an example, the prescaler above can divide by a factor of
11 when the applied control signal is HIGH, or by a factor of 10 when the control
signal is LOW. It can be demonstrated that the dual-modulus prescaler makes it
possible to generate a number of output frequencies that are spaced only by f1 and
not by a multiple of f1.
Integer-N Frequency Synthesizers with Prescalers cont.
http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf
https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-
8#q=an535
http://eprints.lancs.ac.uk/52334/1/PLLbook_chapter_final_2.pdf
http://www.ti.com/lit/ds/symlink/lm565.pdf
PLL-74HC4046_Application_Note%20(1).pdf
http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L170-FreqSy
n-I(2UP).pdf
http://iris.lib.neu.edu/cgi/viewcontent.cgi?article=1007&context=elec_comp_theses
References:
http://www.scribd.com/doc/237983665/PLL
http://www.seas.ucla.edu/brweb/teaching/215C_W2013/PLLs.pdf
http://www.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf
http://www.ti.com/lit/an/snoa351/snoa351.pdf
http://memo.cgu.edu.tw/jtkuo/files/eelab%202014%28III%29/1230_Lab1
2_Expxx_PhaseLockedLoop.pdf
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http://ecee.colorado.edu/~ecen4618/lab4.pdf