2

2.1 2.11
2.2 2.12 C
2.3
2.4 2.13 C
2.5 2.14 ARMv7 (32 )
2.6 2.15 x86
2.7 2.16 ARMv8 (64 )
2.8 2.17
2.9 MIPS 32 2.18
2.19
2.10
2.1
(instructions)
(instructionset)
MIPS Technologies





(stored-program concept)2.1

2 3
2.1 MIPS 3-1

2 4
2.1 MIPS 3-2

2 5
2.1 MIPS 3-3

2 6
2.2
MIPS

add a, b, c # b c a
MIPS




(simplicity favors
regularity)

2 7
2.3

(registers)
32

MIPS 32
32
MIPS (word)

2 8
2.3
(smaller is faster)

2 9
C

f=(g+h)-(i+j)
fghij $s0$s1$s2
$s3$s4
MIPS

2 10
C

add $t0, $s1, $s2 # $t0 g+h

add $t1, $s3, $s4 # $t1 i+j
sub $s0, $t0, $t1 # f $t0-$t1, (g+h)-(i+j)

2 11



MIPS

(data transfer
instrudions)

(load)
lw(load word)

2 12


(allocate)


MIPS
4
MIPS 4
(alignment restriction)

2 13




(store)
sw(store word)

2 14


2 15



0
MIPS $zero 0

2 16
2.4
i
d i
i 0
11
MIPS
10112

(least significant bit)

(0)(most
significant bit) (31)
2 17


(overflow)

(sign and magnitude)

2(two's complement)
2

1(one's complement)
(biased notation)
(bias)
2 18

Loads
(sign extension)

2 19
2.5

MIPS
MIPS

add $t0,$s1,$s2
MIPS

2 20
MIPS

0 17 18 8 0 32

(field)
(0 32)
MIPS
(source operand)
(17=$s1)
(18=$s2)
(8=$t0)
0 $s1 $s2
$t0
2 21
MIPS

000000 10001 10010 01000 00000 100000

6 5 5 5 5 6

2 22
2.5
(instruction
format)

MIPS 32

(machine
language)

2 23
MIPS
MIPS
op rs rt rd shamt funct
6 5 5 5 5 6

MIPS
op
(opcode)
rs
rt
rd

2 24
MIPS
shamt(shift amount)(2.6

0)
funct(function
code)op
(variant)

2 25
MIPS
(good
design demands good compromises)
MIPS

R (register)R
I (immediate) I
I

op rs rt
6 5 5 16

2 26
 MIPS

2.6 2.5 MIPS

R I MIPS op
rs rt rt
R rd shamt 2.6 funct
R I address
2 27

1.
2.

(stored-program)
2.7
(editor)
(compiled)
(text)

2 28
 2.7

2 29
2.6

2.8 C JAVA MIPS

MIPS 0 NOR NOT

2 30
2.7
MIPS
if go to
beq register 1, register 2 L1

bne register 1, register 2, L1

(conditional branches)

2 31

(basic block)



(phases)

2 32


(set on less than)
slt $t0,$s3,$s4 # $s3<s4 $t0=1

slti $t0,$s2,10 # $s2<10 $t0=1

2 33
Case/Switch( )
switch
switch if-then-else


(jump address table)(jump table)



MIPS
(jump register, jr)

2 34
2.8

1.
2.
3.
4.
5.
6.

2 35
2.8


MIPS 32

$a0-$a34 (argument)

$v0-$v12 (value)
$ra1 (return
address)

2 36
2.8
MIPS

$ra
(jump-and-link, jal)
jal ProcedureAddress

$ra(31)(link)
(return address)

(jump register, jr)
jr $ra

2 37



(stack)
MIPS 29

2 38



$t0-$t910
(callee)
$s0-$s78
(saved registers)(
)

2 39


2 40




($a0-$a3)($t0-$t9)


(saved registers, $s0-$s7)

2.11

2 41
2.11

(frame pointer register)

2 42


(procedure frame)
(activation record)
MIPS (frame pointer,
$fp)

2 43
(Heap)
C

2.13 MIPS


MIPS
(text segment)
(static data segment)

2 44
(Heap)
(linked lists)

(heap)

2.14 MIPS

2 45
2.14 MIPS
1 $at(2.12 )26-27 $k0-
$k1MIPS

2 46
2.9 MIPS 32

32
(load upper immediate, lui)

2 47
32

32 $s0 MIPS
0000 0000 0011 1101 0000 1001 0000 0000

2 48
32

lui 16 6110

lui $s0, 61 # 6110=0000 0000 0011 11012

$s0
0000 0000 0011 1101 0000 0000 0000 0000
16 230410
ori $s0, $s0, 2304 # 230410=0000 1001 0000 0000
$s0
0000 0000 0011 1101 0000 1001 0000 0000

2 49

MIPS J(jump)

2 10000
6 26

MIPS
PC-
(jump-and-link)

2 50

MIPS
J(jump)
PC-

26
MIPS PC 28
4

2 51
MIPS
2.16
MIPS
(immediate addressing)

(register addressing)
()
(base or displacement
addressing)

2 52
MIPS
PC (PC-relative addressing)
PC
(pseudodirect addressing)
26 (26
)PC

2 53
2.16 MIPS

3
2



1
16
4 5

4 16
2 PC
5 2
26 PC
4

2 54
 116

2 55
 2

2 56
 3

2 57
 4 5 4
16 2 PC5
226 PC 4

2 58

2.17 MIPS

2 59
2.17 MIPS
load word 4 (31-29
1002)3(28-26 0112)op (31-26 )1000112
0 0 (op=0000002)R 4 2 subtract
funct (5-0)1000102 op (31-26)00000022 1 floating point
3.18 Bltz/gez A 4 bltzbgezbltzal bgezal
A
2 60

2.18 MIPS

2.18 MIPS

2 61
2.10
(lock)(unlock)

(mutual exclusion)


(atomically)
(primitives)

2 62
2.10
(atomic
exchange atomic swap)

lock0
1
lock 1()
1 lock

1

0lock 1
lock 0
2 63
2.10



MIPS (load
linked) (store conditional)
load linked
load linked store
conditional store conditional

store conditional

10

2 64



(processes)
()
(context switch)
()

(atomic compare and swap)
(atomic fetch-and-
increment)
ll sc

2 65
2.11
C

2.19

2 66

C

2 67







(pseudoinstructions)
MIPS ()
move $t0,$t1 # $t0 $t1()

2 68



add $t0,$zero,$t1 # $t0 0+$t1()
blt()(slt
bne )bgt()bge()
ble()16
MIPS32
()
MIPS

$at
2 69


(object file)


(symbol table)

2 70

UNIX
(object file header)
(text segment)
(static data segment)
(relocation information)

(debugging information)

2 71

(link editor)(linker)



(

loader )


()

2 72







(executable file)

2 73



UNIX (loader)
1.

2. ()

3.
4.

2 74

5.

6.

exit

2 75









C
2.5 MB

2 76

(dynamically linked libraries,
DLLs)

DLLs

(indirection)2.20

2 77
2.20

(a)DLL
(b)
DLL

2 78
2.12 C
swap

2.21 C

2 79
swap

2 80
swap
MIPS $a0$a1
$a2 $a3
swap v k $a0
$a1
tempswap
$t0

2 81
swap

2 82
swap

2.22 2.21 swap MIPS

2 83
sort
(bubble)(exchange)

2.23 v C

2 84
sort
v n $a0 $a1
$s0 $s1 i j

2 85
sort
for
swap
for

for

2 86
sort

2 87
sort
for C

for

2 88
sort

2 89
sort
for
swap(v, j);
jal swap

2 90
sort
sort $a0 $a1
swap

$a0 $a1 $s2
$s3

swap

2 91
sort
sort
$ra
sort $s0$s1$s2 $s3


sort

2 92
sort

jr

2 93
sort

2.24 2.23 sort MIPS

2 94
 2.24 2.23 sort MIPS
2 95
 2.24 2.23 sort MIPS

2 96

(procedure
inlining)
()4

2 97


2.25 CPI
100,000
3.06GHz Pentium 4 533 MHz 2 GB PC2100 DDR
(SDRAM)Linux 2.4.20

2 98


2.26 C

Quicksort Bubble Sort

2.25

2 99
2.13 C
C

2 100
2.14 ARMv7(32 )
2.27 ARM MIPS
MIPS
ARM

2.27 ARM MIPS

2 101


2.29
ARM +
0 ARM
1 2
2 102

MIPS
ARM
(program status word)(condition
code bits)(negative)(zero)(carry)
(overflow)
ARM

2.30 ARM MIPS

2 103
2.30
ARM
MIPS

16
32

2 104
ARM
2.31 MIPS

2.31 MIPS ARM

2 105
ARM
ARM
(block loads and stores)
16

2 106
2.15 x86
Intel x86
x86

2 107
x86
2.32 80386

80386
8
32

2 108
x86

2.33

x86
816 32
2.32 14 (
EIP EFLAGS)

2 109
x86

2.34 x86 32 MIPS

ARM MIPS
4(2)(2.25 2.27)1 16 3 64
0 16
MIPS lui 16 add 16
$s1 (lntel
)
2 110
x86
8086 8 ()16 ()

80386 x86 32 (
double words)
x86
movepushpop
test

(control flow)

(string)
2 111
 x86

2.35 x86
2.36 CALL EIP (Intel
EIP PC)
2 112
 x86

2.36 x86

2 113
x86

2.36 x86

2 114
x86
80386


15

2 115
 2.37 x86

2 116
2.37 x86
2.38 1 w
(double word)MOV
d
ADD 32 32
8 32 TEST
32 32 8
1 17
1 4
4 2

(scaled index mode specifier)

2 117
x86
x86
x86

Intel

2 118
2.16 ARMv8(64 )
2013
ARM
MIPSARMv7

()v7

12 v7

ARM Load Multiple Store Multiple
PC ()

2 119
2.16 ARMv8(64 )
ARM MIPS

V8 32
MIPS
0load store

ARMv8
ARMv7
ARMv7 divide
MIPS branch if equal branch if not equal

2 120
2.17

2 121
2.17



1
(automatic variable)
(pointer)

2 122
2.18
(stored-program)


1.
2.
3.




2 123
2.19
(ISAs)


(reduced instruction set computer)

2 124