CHAPTER TWO

COMPUTER SYSTEM

2.1 MEMORY SYSTEMS

1 6/23/2017
 Computer System
A computer system consists of a processor,
memory, I/O, and the interconnections among
these major components.
The functional behavior of the system consists of
the exchange of data and control signals among
these components.
To support this exchange these components must
be interconnected.

2 6/23/2017
 Computer Components

3 6/23/2017
 Computer Component
Virtually all contemporary computer designs are based on
concepts referred to as von Neumann architecture.
Von Neumann architecture is based on three
key concepts.
Data and instructions are stored in a single read-
write memory.
Contents of this memory are addressable by location,
without regard to the type of data contained there.
Execution occurs in a sequential fashion from one
instruction to the next.

4 6/23/2017
 Computer Component
CPU exchanges data with memory. For this purpose, it
typically makes use of two internal registers:
A memory address register (MAR), which specifies
the address in memory for the next read or write.
A memory buffer register (MBR), which contains the
data to be written into memory or receives the data
read from memory.
Similarly, an I/O address register(I/OAR) specifies a
particular I/O device.
An I/O buffer (I/OBR) register is used for the exchange of
data between an I/O module and the CPU.
An I/O module transfers data from external devices to CPU
and memory, and vice versa.

5 6/23/2017
 Computer Function
The basic function performed by a computer is execution of
a program
Which consists of a set of instructions stored in memory.
In its simplest form, instruction processing consists of two
steps:
1. The processor reads (fetches) instructions from
memory one at a time and
2. executes each instruction.
Program execution consists of repeating the process of
instruction fetch and instruction execution.
The processor required for a single instruction is called an
instruction cycle.

6 6/23/2017
 Computer Function
At the beginning of each instruction cycle, the
processor fetches an instruction from memory.
In a typical processor, a register called the program
counter (PC) holds the address of the instruction to be
fetched next.
The processor always increments the PC after each
instruction fetch so that it will fetch the next
instruction in sequence.
The fetched instruction is loaded into a register in the
processor known as the instruction register (IR).
The instruction contains bits that specify the action the
processor is to take.
The processor interprets the instruction and performs
the required action.
7 6/23/2017
 Computer Function
Virtually all computers provide mechanism by which
other modules (I/O, memory) may interrupt normal
processing of processor.
Interrupts are provided primarily as a way to improve
processing efficiency.
The most common classes of interrupts:
Program: Occurs as a result of an instruction execution, such
as arithmetic overflow, division by zero, etc.
Timer: Generated by a timer within the processor and allows
the operating system to perform certain functions on a regular
basis.
I/O: Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety of error
conditions.
Hardware failure: Generated by a failure such as power
failure or memory parity error.
8 6/23/2017
 Computer Function
From the point of view of the user program, an
interrupt is just an interruption of the normal sequence
of execution.
When the interrupt processing is completed, execution
resumes.
To accommodate interrupts, an interrupt cycle is added
to the instruction cycle.
In the interrupt cycle, the processor checks to see if
any interrupts have occurred, indicated by the presence
of an interrupt signal.
If no interrupts are pending, the processor proceeds to
the fetch cycle and fetches the next instruction of the
current program.

9 6/23/2017
 Computer Function
If an interrupt is pending, the processor does the following:
It suspends execution of the current program being
executed and saves its context on the system stack a
special place in memory.
It sets the program counter to the starting address of an
interrupt handler routine.

10 6/23/2017
 2.1 Memory System
No one technology is optimal in satisfying the memory
requirements for a computer system.
As a consequence, the typical computer system is
equipped with a hierarchy of memory subsystems:
Some internal to the system (directly accessible by the
processor) and
Some external to the system (accessed by the
processor via an I/O module).

11 6/23/2017
 2.1 Memory System
What do we need?
A memory to store very large programs and to work
at a speed comparable to that of the CPU.
The reality is:
The larger a memory, the slower it will be;
The faster a memory, the greater the cost per bit.
A solution:
To build a composite memory system which combines
a small and fast memory with a large and slow
memory, and behaves, most of the time, like a large
and fast memory.
This two-level principle can be extended to a
hierarchy of many levels.
12 6/23/2017
 2.1 Memory System
Computer memory is organized into a hierarchy. At the
highest level (closest to the processor) are the processor
registers.
Next comes one or more levels of cache, When multiple
levels are used, they are denoted L1, L2, and so on.
Next comes main memory, which is usually made out of
dynamic random-access memory (DRAM). All of these
are considered internal to the computer system.
The hierarchy continues with external memory, with the
next level typically being a fixed hard disk, and one or
more levels
below that consisting of removable media such as optical
disks and tape.

13 6/23/2017
 Memory hierarchy
The design constraints on a computers memory can be summed
up by three questions:
How much?
How fast?
How expensive?
As might be expected, there is a trade-off among the three key
characteristics of memory: namely,
Capacity
access time
cost.

14 6/23/2017
 Memory hierarchy
A variety of technologies are used to implement memory
systems, and across this spectrum of technologies, the
following relationships hold:
Faster access time, greater cost per bit
Greater capacity, smaller cost per bit
Greater capacity, slower access time

As one goes down the hierarchy, the following occur:

Decreasing cost per bit
Increasing capacity
Increasing access time
Decreasing frequency of access of the memory by the processor

15 6/23/2017
 Memory Hierarchy - Diagram

16 6/23/2017
 Hierarchy List
Registers
L1 Cache
L2 Cache
Main memory
Disk
Optical
Tape

17 6/23/2017
 Access methods
Sequential
Start at the beginning and read through in order
Access time depends on location of data and previous location
e.g. tape
Direct
Individual blocks have unique address
Access is by jumping to vicinity plus sequential search
Access time depends on location and previous location
e.g. disk

18 6/23/2017
 Access method
Random
Individual addresses identify locations exactly
Access time is independent of location or previous access
e.g. RAM
Associative
Data is located by a comparison with contents of a portion of
the store
Access time is independent of location or previous access
e.g. cache

19 6/23/2017
 Memory classification
Main memory:
Memory is the workspace for the computers processor.
It holds the instructions that the processor executes and the data
that those instructions work with.
It is a temporary storage area where the programs and data being
operated on by the processor must reside.
Memory storage is considered temporary because the data and
programs remain there only as long as the computer has electrical
power or is not reset.
When we talk about a computers memory, we usually mean the
RAM or physical memory in the system, which is mainly the
memory chips or modules the processor uses to store primary
active programs and data.

20 6/23/2017
 Memory classification
Physically, the main memory in a system is a collection of chips or
modules containing chips that are usually plugged into the
motherboard.
These chips or modules vary in their electrical and physical
designs and must be compatible with the system into which they
are being installed to function properly.
Three main memory plays a significant role in the following
important aspects of your computer system:
Performance
Software Support
Reliability and Stability
Upgradability

21 6/23/2017
 Cont
1. RAM (random access memory)
Holds data and instructions used by CPU
Volatile (unlike ROM, the contents of RAM are lost when the
power is turned off).
RAM is also sometimes called read-write memory or RWM.
RAM is much faster than ROM.
RAM is stored in modules: DIMMs, RIMMs, SIMMs
There are many different types of RAMs:
static RAM (SRAM) and
dynamic RAM (DRAM)
Memory cache is made up of SRAM (it is faster)

22 6/23/2017
 Static RAM
It holds its data without external refresh, for as long as power is supplied
to the circuit.
SRAM is much faster than DRAM and much more capable of keeping
pace with modern processors.
SRAM memory is available in access times of 2ns or less, so it can keep
pace with processors running 500MHz or faster.
SRAMs are much lower in density(SRAM chips are physically larger and
store fewer bits overall) and much more expensive than DRAMs,
SRAM is up to 30 times larger physically and up to 30 times more
expensive than DRAM.
SRAM is manufactured in a way rather similar to how processors are:
highly-integrated transistor patterns photo-etched into silicon.
Each SRAM bit is comprised of between four and six transistors, which
is why SRAM takes up much more space compared to DRAM, which
uses only one (plus a capacitor).

23 6/23/2017
 Strength and Weakness of SRAM
Strengths:
Simplicity: SRAMs don't require external refresh circuitry or
other work in order for them to keep their data intact.
Speed: SRAM is faster than DRAM.
Weaknesses:
Cost: SRAM is several times more expensive than DRAM.
Size: SRAMs take up much more space than DRAMs.
Cache memory is a type of SRAM memory, which can run fast
enough to match the CPU,
Three types: L1,L2,L3(L1 is the fastest)

24 6/23/2017
 Dynamic RAM
Dynamic RAM is a type of RAM that only holds its data if it is
continuously accessed by special logic called a refresh circuit.
The memory cells in a DRAM chip are tiny capacitors that retain a
charge to indicate a bit.
DRAM must be constantly refreshed; otherwise, the electrical
charges in the individual memory capacitors will drain and the
data will be lost even if it continues to have power supplied to it.
Refresh occurs when the system memory controller takes a tiny
break and accesses all the rows of data in the memory chips.
Refreshing the memory takes processor time away from other tasks
because each refresh cycle takes several CPU cycles to complete.
DRAMs use only one transistor and capacitor pair per bit, which makes
them very dense, offering more memory capacity per chip than other
types of memory.

25 6/23/2017
 Cont
The transistor for each DRAM bit cell reads the charge state of the
adjacent capacitor.
If the capacitor is charged, the cell is read to contain a 1; no charge
indicates a 0.
The charge in the tiny capacitors is constantly draining, which is
why the memory must be refreshed constantly.
The problem with capacitors is that they only hold a charge for a
short period of time, and then it fades away.
DRAMs are inexpensive, slow and the chips can be densely
packed, so a lot of memory capacity can fit in a small space.
Currently, DRAM chips are available with densities of up to 1Gb or
more. This means that DRAM chips are available with one billion or more
transistors!

26 6/23/2017
 Cont
2. ROM (read-only memory)
Is a type of memory that can permanently or semi-permanently
store data.
Non-volatile (retains data after PC is turned off)
The fact that ROM cannot easily be modified provides a measure of
security against accidental (or malicious) changes to its contents.
ROM is an ideal place to put the PCs startup instruction. i.e. the
software that boots the system.
The main ROM BIOS is contained in a ROM chip on the
motherboard, but there are also adapter cards with ROMs on them
as well.
ROMs on adapter cards contain auxiliary BIOS routines and drivers
needed by the particular card, especially for those cards that must
be active early in the boot process, such as video cards.

27 6/23/2017
 ROM Types
A. ROM: is designed to perform a specific function and cannot be
changed.
This is inflexible and so regular ROMs are only used generally
for programs that are static (not changing often) and mass-
produced.
B. Programmable ROM (PROM): can be programmed using
special equipment; it can be written to, but only once.
C. Erasable Programmable ROM (EPROM): is a ROM that can
be erased and reprogrammed.
Ultraviolet light of a specific frequency can be shined through
this window for a specified period of time, which will erase
the EPROM and allow it to be reprogrammed again

28 6/23/2017
 Cont
D. Electrically Erasable Programmable ROM (EEPROM): is ROM
that can be erased and reprogrammed under software control.
This is the most flexible type of ROM, and is now commonly
used for holding BIOS programs.
When you hear reference to a flash BIOS or doing a BIOS
upgrade by "flashing", this refers to reprogramming the BIOS
EEPROM with a special software program.
Any location can be read from ROM in any order, so it is random
access as well.
Finally, one other characteristic of ROM, compared to RAM, is
that it is much slower, typically having double the access time of
RAM or more.

29 6/23/2017
 Memory classification
Cache: A small, very fast, memory used to store data and
instructions, that have recently been used or are likely to be
used soon.
When a byte of memory is retrieved by the Memory
Management Unit (MMU), a copy of that byte and a number
of other nearby bytes are placed in the cache.
Sits between normal main memory and CPU

30 6/23/2017
 Cache memory levels
Modern systems often contain several levels of cache:
L1 Cache:
On the CPU chip.
Smallest and fastest cache.
L2 Cache:
Larger and slower than L1 cache.
L3 Cache:
Larger and slower than L2 cache.

31 6/23/2017
 Element of Cache design
There are a few basic design elements that serve to classify
and differentiate cache architectures:

32 6/23/2017
 Mapping
The transfer of data from main memory to cache memory is
referred as mapping process.
There are three types of cache mapping:
1. Direct Mapping: maps each block of main memory into
only one possible cache line.
2. Fully Associative Mapping: permits each main memory
block to be loaded into any line of the cache.
3. Set Associative Mapping: the cache is divided into a number
of sets of cache lines; each main memory block can be
mapped into ant line in a particular set.

33 6/23/2017
 Replacement algorithms
When all lines are occupied bringing in a new block
requires that an existing line be overwritten.
There are four most common algorithms:
1. Least-recently-used (LRU): The idea is to replace that block
in set which has been in cache longest with no reference to it.
2. First-in-first-out (FIFO): The idea is to replace that block in
set which has been in cache longest.
3. Least-frequently-used (LFU): The idea is to replace that
block in set which has experienced fewest references.
4. Random: The idea is to replace a random block in set.

34 6/23/2017
 Write Policy
The problem:
How to keep cache content and main memory content
consistent without losing too much performance?
The are mostly two techniques to overcome these problems:
Write through:
All write operations are passed to main memory:
If the addressed location is currently in the cache, the cache is
updated so that it is coherent with the main memory.
Write back:
Write operations update only the cache memory which is not kept
coherent with main memory. When the slot is replaced from the
cache, its content has to be copied back to memory.

35 6/23/2017
 Secondary memory

Figure. Hard disk construction and Operation

36 6/23/2017
 Secondary memory
Disk storage:-
Disks are workhorse storage devices that hold enormous
amounts of data.
Disk Geometry:-
Disks are constructed from platters. Each platter consists of
two sides, or surfaces, that are coated with magnetic recording
material.
A rotating spindle in the center of the platter spins the platter
at a fixed rotational rate, typically between 5400 and 15,000
revolutions per minute (RPM).

37 6/23/2017
 Cont
Each surface consists of a collection of concentric
rings called tracks.
Each track is partitioned into a collection of sectors.
Each sector contains an equal number of data bits (typically
512 bytes) encoded in the magnetic material on the sector.
Sectors are separated by gaps where no data bits are stored.
Gaps store formatting bits that identify sectors.

38 6/23/2017
39 6/23/2017
 Cont

Disk geometry

40 6/23/2017
41 6/23/2017
 Cont
Disk manufacturers describe the geometry of multiple-
platter drives in terms of cylinders, where a cylinder is the
collection of tracks on all the surfaces that are equidistant
from the center of the spindle.
For example, if a drive has three platters and six surfaces, and
the tracks on each surface are numbered consistently, then
cylinder k is the collection of the six instances of track k.

42 6/23/2017
 Disk Capacity
The maximum number of bits that can be recorded by a disk
is known as its maximum capacity, or simply capacity.
Disk capacity is determined by the following technology
factors:
Recording density (bits/in): The number of bits that can be
squeezed into a 1-inch segment of a track.
Track density (tracks/in): The number of tracks that can be
squeezed into a 1-inch segment of the radius extending from
the center of the platter.

43 6/23/2017
 Cont
Areal density (bits/in2): The product of the recording density
and the track density.
The capacity of a disk is given by the following formula:

44 6/23/2017
 Disk Operation
Disks read and write bits stored on the magnetic surface
using a read/write head connected to the end of an actuator
arm.
By moving the arm back and forth along its radial axis, the
drive can position the head over any track on the surface. This
mechanical motion is known as a seek.

45 6/23/2017
 Cont

46 6/23/2017
 Cont
Disks read and write data in sector-sized blocks.
The access time for a sector has three main components:
seek time,
rotational latency
transfer time:

47 6/23/2017
 CHAPTER TWO part 2

2.2 INPUT OUTPUT SYSTEM

48 6/23/2017
 Introduction
The computer systems I/O architecture is its interface to
the outside world.
This architecture provides a systematic means of controlling
interaction with the outside world and provides the operating
system with the information it needs to manage I/O activity
effectively.
The are three principal I/O techniques:
programmed I/O
interrupt-driven I/O
direct memory access (DMA)

49 6/23/2017
 Introduction
programmed I/O, in which I/O occurs under the direct and
continuous control of the program requesting the I/O operation.
interrupt-driven I/O, in which a program issues an I/O
command and then continues to execute, until it is interrupted by
the I/O hardware to signal the end of the I/O operation.
direct memory access (DMA), in which a specialized I/O
processor takes over control of an I/O operation to move a large
block of data.
Two important examples of external I/O interfaces are:
FireWire
Infiniband.

50 6/23/2017
 Input output devices
There are a wide variety of peripherals with various methods
of operation.
It would be impractical to incorporate the necessary logic
within the processor to control a range of devices.
The data transfer rate of peripherals is often much slower
than that of the memory or processor.
Thus, it is impractical to use the high-speed system bus to
communicate directly with a peripheral.

51 6/23/2017
 Cont
On the other hand, the data transfer rate of some peripherals
is faster than that of the memory or processor.
Again, the mismatch would lead to inefficiencies if not
managed properly.
Peripherals often use different data formats and word lengths
than the computer to which they are attached.

52 6/23/2017
 Purpose of I/O Modules
Interface to the processor and memory via the system bus or
control switch.
Interface to one or more peripheral devices.

53 6/23/2017
 External Devices
An external device connected to an I/O module is often
referred to as a peripheral device or, simply, a peripheral.
External device categories:
Human readable: communicate with the computer user
VDT, printers etc.
Machine readable: communicate with equipment disk
drive or tape drive
Communication: communicate with remote devices may
be human readable or machine readable

54 6/23/2017
 The External Device I/O Module
The interface to the I/O module is in the form of control, data,
and status signals.
Control signals determine the function that the device will perform,
such as send data to the I/O module (INPUT or READ), accept
data from the I/O module (OUTPUT or WRITE), report status,
or perform some control function particular to the device (e.g.,
position a disk head).
Data are in the form of a set of bits to be sent to or received from
the I/O module.
Status signals indicate the state of the device. Examples are
READY/NOT-READY to show whether the device is ready for
data transfer.

55 6/23/2017
 Cont
Control logic associated with the device controls the devices
operation in response to direction from the I/O module.
The transducer converts data from electrical to other forms of
energy during output and from other forms to electrical
during input.
Typically, a buffer is associated with the transducer to
temporarily hold data being transferred between the I/O
module and the external environment.

56 6/23/2017
 Block Diagram of an External Device

57 6/23/2017
 Keyboard/Monitor
Most common means of computer/user interaction
Keyboard provides input that is transmitted to the computer
Monitor displays data provided by the computer
The character is the basic unit of exchange
Each character is associated with a 7 or 8 bit code

58 6/23/2017
 Disk Drive
Contains electronics for exchanging data, control, and status
signals with an I/O module
Contains electronics for controlling the disk read/write
mechanism
Fixed-head disk transducer converts between magnetic
patterns on the disk surface and bits in the buffer
Moving-head disk must move the disk arm rapidly across
the surface

59 6/23/2017
 Interconnection Structures
The collection of paths connecting the various modules is
called the Interconnection structure.
Supports the following types of transfers:
Memory to CPU: Processor reads an instruction or a unit of
data from memory.
CPU to memory: Processor writes a unit of data to memory.
I/O to CPU: Processor reads data from an I/O device.
CPU to I/O: Processor sends data to an I/O device.
I/O to or from memory: An I/O module is allowed to
exchange directly with memory, without going through
processor, using Direct Memory Access (DMA).
The most common types of interconnection structure is the
BUS.
60 6/23/2017
 Bus Interconnection
A bus is a communication pathway connecting two or
more devices. A key characteristic of a bus is that it is a
shared transmission medium.
Typically, a bus consists of multiple communication
pathways, or lines. Each line is capable of transmitting
signals representing binary 1 and binary 0.
A bus that connects major computer components
(processor, memory, I/O) is called a system bus.

61 6/23/2017
 Bus Interconnection
Bus Structure
A system bus consists, typically, of from about 50 to
hundreds of separate lines. Each line is assigned a particular
meaning or function.
Generally the bus has three functional groups: Data, address,
and control lines(bus).

62 6/23/2017
 Bus Interconnection
Data lines: collectively are called the data bus.
Transfers data from different computer system components
the width of the data bus is a key factor in determining overall
system performance.
Address lines: are used to designate the source or destination
of the data on the data bus.
The width of the address bus determines the maximum possible
memory capacity of the system.
Control lines: are used to control the access to and the use of
the data and address lines.
Because the data and address lines are shared by all
components, there must be a means of controlling their use.
63 6/23/2017
 Bus Interconnection
Typical control lines includes:
Memory write: Causes data on the bus to be written into the addressed location.
Memory read: Causes data from the addressed location to be placed on the bus.
I/O write: Causes data on the bus to be output to the addressed I/O port.
I/O read: Causes data from the addressed I/O port to be placed on the bus.
Transfer ACK: Indicates that data have been accepted from or placed on the bus.
Bus request: Indicates that a module needs to gain control of the bus.
Bus grant: Indicates that a requesting module has been granted control of the
bus.
Interrupt request: Indicates that an interrupt is pending.
Interrupt ACK: Acknowledges that the pending interrupt has been recognized.
Clock: Is used to synchronize operations.
Reset: Initializes all modules

64 6/23/2017
 Bus Interconnection
The operation of the bus:
If one module wishes to send data to another, it must do two
things:
obtain the use of the bus
transfer data via the bus
If one module wishes to request data from another module,
it must:
obtain the use of the bus
transfer a request to the other module over the
appropriate control and address lines
it must then wait for that second module to send the data

65 6/23/2017
 I/O Modules
Module Functions are:
Control and timing
Processor communication
Device communication
Data buffering
Error detection

66 6/23/2017
 I/O control steps
Processor checks I/O module for external device status
I/O module returns status
If device ready, processor gives I/O module command to
request data transfer
I/O module gets a unit of data from device
Data transferred from the I/O module to the processor

67 6/23/2017
 Processor communication
Command decoding: I/O module accepts commands
from the processor sent as signals on the control bus.
Examples: READ SECTOR, WRITE SECTOR, SEEK track
number, and SCAN record ID.
Data: data exchanged between the processor and I/O
module over the data bus
Status reporting: common status signals BUSY and
READY are used because peripherals are slow
Address recognition: I/O module must recognize a
unique address for each peripheral that it controls

68 6/23/2017
 I/O module communication
Device communication: commands, status information,
and data
Data buffering: data comes from main memory in rapid
burst and must be buffered by the I/O module and then sent
to the device at the devices rate
Error detection: responsible for reporting errors to the
processor. They may include:
Malfunctions by device (paper jam)
Data errors (parity checking at the device level)
Internal errors to the I/O module such as buffer overruns

69 6/23/2017
 Typical I/O Device Data Rates

70 6/23/2017
 I/O Module Structure

Block Diagram of an I/O Module

71 6/23/2017
 Cont
I/O module functions allow the processor to view devices is
a simple-minded way
I/O module may hide device details from the processor so
the processor only functions in terms of simple read and
write operations timing, formats, etc
I/O module may leave much of the work of controlling a
device visible to the processor rewind a tape, etc

72 6/23/2017
 I/O Techniques
Programmed
Interrupt driven
Direct Memory Access (DMA)

73 6/23/2017
 Programmed I/O

Processor executes an I/O instruction by issuing command

to appropriate I/O module
I/O module performs the requested action and then sets the
appropriate bits in the I/O status register I/O module
takes not further action to alert the processor it does not
interrupt the processor
The processor periodically checks the status of the I/O
module until it determines that the operation is complete

74 6/23/2017
 I/O Commands
The processor issues an address, specifying I/O module and
device, and an I/O command. The commands are:
Control: activate a peripheral and tell it what to do
Test: test various status conditions associated with an I/O
module and its peripherals
Read: causes the I/O module to obtain an item of data from
the peripheral and place it into an internal register
Write: causes the I/O module to take a unit of data from the
data bus and transmit it to the peripheral

75 6/23/2017
 Three Techniques for Input of a Block
of Data

76 6/23/2017
 Interrupt-Driven I/O
Overcomes the processor having to wait long periods of time for I/O
modules
The processor does not have to repeatedly check the I/O module status
To avoid the processor being not performing an useful computation, a
hardware signal called an interrupt to the processor can do it.
At least one of the bus control lines, called an interrupt-request line, is
usually dedicated for this purpose
An interrupt-service routine usually is needed and is executed when an
interrupt request is issued
On the other hand, the processor must inform the device that its
request has been recognized so that it may remove its interrupt-request
signal.
An interrupt-acknowledge signal serves this function

77 6/23/2017
 I/O module view point
I/O module receives a READ command form the processor
I/O module reads data from desired peripheral into data
register
I/O module interrupts the processor
I/O module waits until data is requested by the processor
I/O module places data on the data bus when requested

78 6/23/2017
 Processor view point
The processor issues a READ command
The processor performs some other useful work
The processor checks for interrupts at the end of the
instruction cycle
The processor saves the current context when interrupted by
the I/O module
The processor read the data from the I/O module and stores
it in memory
The processor the restores the saved context and resumes
execution

79 6/23/2017
 Design Issues
How does the processor determine which device issued the
interrupt
How are multiple interrupts dealt with
Device identification
Multiple interrupt lines each line may have multiple I/O
modules
Software poll poll each I/O module
Separate command line TESTI/O
Processor read status register of I/O module
Time consuming

80 6/23/2017
 Cont
Daisy chain
Hardware poll
Common interrupt request line
Processor sends interrupt acknowledge
Requesting I/O module places a word of data on the data
lines vector that uniquely identifies the I/O module
vectored interrupt

81 6/23/2017
 Cont
Bus arbitration
I/O module first gains control of the bus
I/O module sends interrupt request
The processor acknowledges the interrupt request
I/O module places its vector of the data lines

82 6/23/2017
 Cont
Multiple interrupts
The techniques above not only identify the requesting I/O
module but provide methods of assigning priorities
Multiple lines processor picks line with highest priority
Software polling polling order determines priority
Daisy chain daisy chain order of the modules determines
priority
Bus arbitration arbitration scheme determines priority

83 6/23/2017
 Direct Memory Access
To transfer large blocks of data at high speed, a special
control unit may be provided between an external device and
the main memory, without continuous intervention by the
processor.
This approach is called direct memory access (DMA)
DMA transfers are performed by a control circuit that is part
of the I/O device interface.
We refer to this circuit as a DMA controller.

84 6/23/2017
 Direct Memory Access
Drawback of Programmed and Interrupt-Driven I/O
I/O transfer rate limited to speed that processor can test
and service devices
Processor tied up managing I/O transfers
DMA Controller Function
.DMA controller requests data bus control from CPU.
CPU grants the data bus control to the DMA controller
DMA controller reads device and writes to memory
DMA controller generates an interrupt request

85 6/23/2017
 Typical DMA Block Diagram

86 6/23/2017
 I/O Interfaces
The External Interface: FireWire and Infiniband
Type of Interfaces
Parallel interface multiple bits transferred simultaneously
Serial interface bits transferred one at a time

87 6/23/2017
 Standard I/O Interfaces
The processor bus is the bus defined by the signals on the
processor chip itself.
Devices that require a very high speed connection to the
processor, such as the main memory, may be connected directly to
this bus
The motherboard usually provides another bus that can support
more devices.
The two buses are interconnected by a circuit, which we called a
bridge, that translates the signals and protocols of one bus into
those of the other
The expansion bus is not subject to these limitations, and
therefore it can use a standardized signaling structure

88 6/23/2017
 Universal Serial Bus (USB)
The USB has been designed to meet several key objectives
Provide a simple, low-cost, and easy to use interconnection
system that overcomes the difficulties due to the limited
number of I/O ports available on a computer
Accommodate a wide range of data transfer characteristics
for I/O devices, including telephone and Internet
connections
Enhance user convenience through a plug-and-play mode of
operation

89 6/23/2017
 FireWire Serial Bus IEEE 1394

Very high speed serial bus

Low cost
Easy to implement
Used with digital cameras, televisions etc.

90 6/23/2017
 Infiniband

Recent I/O specification aimed at high-end server market

First version released early 2001
Standard for data flow between processors and intelligent
I/O devices
Intended to replace PCI bus in servers
Greater capacity, increased expandability, enhanced flexibility
Connect servers, remote storage, network devices to central
fabric of switches and links

91 6/23/2017