Ch7 Sequential

Chapter 7
Sequential Circuits
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
August 20, 2004; Revised - July 4, 2005
B.Supmonchai
Goals of This Chapter

Implementation techniques for
Register: latches and flipflops
Schmitt Triggers
Oscillator, pulse generators
Static versus Dynamic Realization

Clocking Strategies
2102-545 Digital ICs Sequential Logic 2

B.Supmonchai
Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC
Current State Next state

State
Q Register D
CLOCK
Storage Mechanisms
Positive Feedback Charge-Based

STATIC DYNAMIC
B.Supmonchai
Static vs Dynamic Storage

Static storage
preserve state as long as the power is on
have positive feedback (regeneration) with an internal
connection between the output and the input
useful when updates are infrequent (clock gating)
Dynamic storage
store state on parasitic capacitors
only hold state for short periods of time (milliseconds)
require periodic refresh
usually simpler, so higher speed and lower power

B.Supmonchai
Latches versus Flipflops

Latches (with Clock)
level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode
input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode
Flipflops (edge-triggered)
edge sensitive circuits that sample the inputs on a clock
transition
positive edge-triggered: 0 1
negative edge-triggered: 1 0
built using latches (e.g., master-slave flipflops)

B.Supmonchai
Review: The Regenerative Property

Vi1 Vo1 Vi2 Vo2 Small deviation from
bias point C (e.g., from
noise) is amplified and
Cascaded Inverters regenerated around the
circuit loop until either
point A or B is reached
A
If the gain in the
C
transient region is larger
than 1, only A and B are
stable operation points.
B C is a metastable
Vi1 = Vo2 operation point.

B.Supmonchai
Review: Bistable Circuits

The cross-coupling of two Vi1
inverters results in a
bistable circuit (a circuit
with two stable states) Vi2
Have to be able to change the stored value by making A

(or B) temporarily unstable by increasing the loop gain
to a value larger than 1
done by applying a trigger pulse at Vi1 or Vi2
the width of the trigger pulse need be only a little larger than
the total propagation delay around the loop circuit (twice the
delay of an inverter)

B.Supmonchai
Review: SR Latch
S S R Q !Q Action
!Q
0 0 Q !Q memory
1 0 1 0 set
0 1 0 1 reset
Q
R 1 1 0 0 disallowed

B.Supmonchai
Review: Clocked D Latch

D
!Q
D Q
Q
clock
clock transparent mode
In our course
clock All latches mean
clocked latches
hold mode
B.Supmonchai
Latches versus Flipflops II

Latch Flipflop
stores data when stores data when
clock is low (high) clock rises (falls)
D Q D Q
Clk Clk
Clk Clk
D D
Q Q

B.Supmonchai
Positive and Negative Latches

Positive Latch Negative Latch
In D Q Out In D Q Out
G G
Clk Clk
Clk Clk
In In
Out Out
Out Out Out Out Out Out Out Out

Stable Follow In Stable Follow In Stable Follow In Stable Follow In

B.Supmonchai
Latch-Based Design
N latch is transparent P latch is transparent
when f = 0 when f = 1
f
N P
Latch
Logic Latch
Logic

B.Supmonchai
Timing Metrics
clock
clock
tsu thold time
In data
stable
tc-q time
Out output output

stable stable
time
B.Supmonchai
Timing Definitions
Setup time, tsetup is the time that the data inputs
(D) must be valid before the clock transition
0 to 1 transition for a positive edge-triggered device
1 to 0 transition for a negative edge-triggered device
Hold time, thold is the time that the data inputs

must remain valid after the clock edge
Propagation Delay, tc-q is the worst case
propagation delay (with reference to the clock
edge)
time to copy D to Q
B.Supmonchai
System Timing Constraints

Inputs Outputs
COMBINATIONAL
LOGIC
Current State Next state

State
Q Register D
T (clock period)
CLOCK
tcd: contamination delay = minimum delay
tcdreg + tcdlogic thold T tc-q + tplogic + tsu

B.Supmonchai
Notes on System Timing Constraints

It is important to minimize the values of the timing
parameters associated with the register.
In modern high-performance systems, the register
propagation delay and set-up times account for a
significant portion of the clock period.
DEC Alpha EV6 has a maximum logic depth of 12 gates and
the register overhead accounts for about 15% of the clock
period.
Hold time becomes an issue when there is little logic

between registers or when the clocks at different
registers are somewhat out of phase due to clock skew.
B.Supmonchai
Building A (Static) Latch

For a latch, use the clock as a decoupling signal, that
distinguishes between the transparent and opaque states
CLK
CLK
Q D D
CLK
CLK
D
CLK
can implement as NMOS-only
Cutting the feedback loop Overpowering the feedback loop

(Mux-based latch) (as in Static RAM)

B.Supmonchai
MUX Based Latches

Change the stored value by cutting the feedback loop
feedback feedback
1 0
Q Q
D 0 D 1
clk clk
Negative Latch Positive Latch
Q = clk & Q | !clk & D Q = !clk & Q | clk & D

transparent when the transparent when the
clock is low clock is high
B.Supmonchai
TG MUX Based Latch Implementation

clk
Positive Latch
Q
input sampled
!clk
(transparent mode)
D
clk
clk
!clk
clk load is two transistors (and two
for !clk) = clock load of 4
Having to generate both clk and !clk feedback
(nonoverlapping clocks) (hold mode)

B.Supmonchai
PT MUX Based Latch Implementation

clk !Q
D Q
input sampled
(transparent mode)
!clk
clk
Reduced clock load, but !clk

threshold drop at output of
pass transistors so reduced
noise margins and performance feedback
(hold mode)

B.Supmonchai
Latch Race Problem
B
B B
clk
clk Which value of B is stored?
T tc-q + tplogic + tsu

Two-sided clock constraint
Thigh tc-q + tcdlogic

B.Supmonchai
Master Slave Based ET Flipflop

D Q
0
1 Q clk
1
0 QM
D clk
clk
clk D
Slave
Master
QM
clk = 0 transparent hold
clk = 1 hold transparent Q

B.Supmonchai
MS ET Implementation
Master Slave
I2 T2 I3 I5 T4 I6 Q
QM
I1 T1 I4 T3
D 20 Transistors*
8 clock loads
clk * Ignore clk buffer
master transparent master hold

slave hold slave transparent
clk
!clk

B.Supmonchai
MS ET Timing Properties
Assume propagation delays are tpd_inv and tpd_tx, that the
contamination delay is 0, and that the inverter delay to
derive !clk is 0
Set-up time - time before rising edge of clk that D must
be valid
tsu = 3 * tpd_inv + tpd_tx
Propagation delay - time for QM to reach Q

tpd = tpd_inv + tpd_tx
Hold time - time D must be stable after rising edge of clk

thold = 0
B.Supmonchai
Notes on MS ET Timing Properties

Set-up time
How long before the rising edge does D have to be stable such
that QM samples the value reliably?
D has to propagate through I1, T1, I3 and I2 before the rising
edge to ensure that the node voltages on both terminals of T2
are the same value.
Propagation delay time
Since the delay of I2 is included in the set-up time, the output
of I4 is valid before the rising edge of clk, so the delay is
simply the delay through T3 and I6
Hold time
since T1 turns off when the clock goes high, any changes in D
after clk goes high are not seen, so hold time is 0
B.Supmonchai
Set-up Time Simulation

3 Q
2.5
2 QM
Volts
1.5
tsetup = 0.21 ns
1 D clk
0.5
I2 out
0
-0.5
0 0.2 0.4 0.6 0.8 1
Time (ns)
works correctly
B.Supmonchai
Set-up Time Simulation II

3
Q
2.5
2 I2 out
Volts
1.5
tsetup = 0.20 ns
1 D clk
0.5
0 QM
-0.5
0 0.2 0.4 0.6 0.8 1
Time (ns)
Fails! the clock is enabled before the nodes on both sides

of the transmission gate T2 settle to the same value

B.Supmonchai
Propagation Delay Simulation

tc-q (LH) = 160 psec tc-q (HL) = 180 psec
3
2.5
2
1.5
Clk D Q
Volts
1
tc-q (LH) tc-q (HL)
0.5
0
-0.5
0 0.5 1 1.5 2 2.5
Time (ns)
propagation delay is measured from the 50% point

of the clk edge to the 50% point of the Q output
B.Supmonchai
Reduced Load MS ET FF
Clock load per register is important since it directly
impacts the power dissipation of the clock network.
Can reduce the clock load (at the cost of robustness) by
making the circuit ratioed
12 Transistors
clk !clk
I3 4 clock loads
I1
T QM T
D Q
1 2
I2 I4
!clk clk reverse conduction
to switch the state of the master, T1 must be sized to overpower I2

to avoid reverse conduction, I4 must be weaker than I1
B.Supmonchai
Non-Ideal Clocks
Clk and !clk are never perfect inversions of one another
We must generate !clk and route both signals
Variations can exist in the wires used to route the two clock
signals and load capacitances may vary
Non-ideal clocks create skew resulting in clock overlap
1-1 Overlap 0-0 Overlap
clk clk
!clk !clk
Ideal clocks Non-Ideal clocks

B.Supmonchai
Example of Clock Skew Problems

X !clk Q
clk
Race
A I1 I2 P3 I3 I4 !Q
D P1
B
P2 P4
!clk clk
Race condition direct path from D to Q during the short time

when both clk and !clk are high (1-1 overlap)
Undefined state both B and D are driving A when clk and !clk
are both high
Dynamic storage when clk and !clk are both low (0-0 overlap)
B.Supmonchai
Pseudostatic Two-Phase ET FF
X clk2 Q
clk1
A I1 I2 P3 I3 I4 !Q
D P1
B
P2 P4
clk2 dynamic clk1

master transparent storage
slave hold
clk1 master hold

tnon_overlap
slave transparent
clk2

B.Supmonchai
Two Phase Clock Generator

A clk1
clk
B
clk2
clk
clk1
clk2
B.Supmonchai
Power PC Flipflop
clk !clk
1D Q 01
01 10 10
!clk clk
16 Transistors
8 clock loads
master transparent
slave hold clk master hold
slave transparent
!clk

B.Supmonchai
Overpowering The Feedback Loop

Clocked SR Latch
Cross-coupled NANDs
M2 M4
S
Q Q
!Q
clk M6 M8 clk
Q
R M1 M3
S M5 M7 R
This is not used in datapaths any more,

but is a basic building block for memory cell
B.Supmonchai
Ratioed CMOS Clocked SR Latch

off on on off
M2 M4
Q 1 0
1 0 !Q
off ->on off ->on
0 1 clk M6 M8 clk 0 1
M1 M3
on off off on R 1
0 S M5 M7 8 Transistors
off on 2 Clock loads*
* sized
No static power consumption, but a ratioed device

where sizing is critical to ensure proper functionality
M7, M8 must overcome M4 to bring Q low, so must M5, M6
over M2
B.Supmonchai
Sizing Issues
(W/L)2 and 4 = 1.5m/0.25 m
2 (W/L)1 and 3 = 0.5m/0.25 m
1.5
!Q (Volts)
1
so (W/L)5 and 6 > 3
0.5
0
2 2.5 3 3.5 4
(W/L)5 and 6
Output voltage depends on pull-down transistor width

B.Supmonchai
Transient Response
3
!Q S
2 W=0.5 m
!Q (Volts)
W=0.6 m
W=0.7 m
1
W=0.8 m
W=0.9 m
W=1 m
0
0 0.4 0.8 1.2 1.6 2
Time (ns)
Individual device ratio for M5 or M6 must be larger than approx. 6.

Analysis results give 2.26 (instead of 3) since it doesnt take into account
channel length modulation and DIBL (drain induced barrier loading).

B.Supmonchai
6 Transistor CMOS SR Latch

clk clk Problems with noise
margins and static
R S power consumption
due to threshold drop
across pass transistors
Once again, sizing is
clk important - especially
clk M2 M4
Q M5 and M6
M6 S
!Q
R M5
M1 M3 6 Transistors
2 Clock loads

B.Supmonchai
Review: Storage Mechanisms

Static Dynamic
(Positive Feedback) (charge-based)
CLK
CLK
Q
D Q
CLK
D
CLK
CLK
Useful when update is infrequent Simpler, Faster, and Lower Power

B.Supmonchai
Dynamic ET Flipflop
master slave
!clk clk 8 Transistors
4 Clock loads
QM
D T1 I1 T2 I2 Q
C C
1 2
clk !clk
tsu = tpd_tx
master transparent thold = zero
slave hold tc-q = 2 tpd_inv + tpd_tx
clk
!clk master hold

slave transparent

B.Supmonchai
Dynamic ET FF Race Conditions

!clk clk
QM
D T1 I1 T2 I2 Q
C C
1 2
clk !clk
0-0 overlap race condition

clk toverlap0-0 < tT1 + tI1 + tT2
!clk
1-1 overlap race condition
toverlap1-1 < thold

B.Supmonchai
Dynamic Two-Phase ET FF
clk1 clk2
QM
D T1 I1 T2 I2 Q
C C
1 2
!clk1 !clk2
master transparent
slave hold
clk1
tnon_overlap
clk2
master hold
slave transparent

B.Supmonchai
Pseudostatic Dynamic Latch

Robustness considerations limit the use of dynamic FFs
Coupling between signal nets and internal storage nodes can
inject significant noise and destroy the FF state
Leakage currents cause state to leak away with time
Internal dynamic nodes dont track fluctuations in VDD that
reduces noise margins
A simple fix is to make the circuit pseudostatic
clk
Slight increase in delay
(adds to the capacitive
D T1
load) and power
consumption, but it
improves noise immunity
!clk significantly
B.Supmonchai
C2MOS (Clocked CMOS) ET Flipflop

Master Slave
M2 M6
8 Transistors
4 Clock loads
on off
clk M4 !clk M8
QM
D off on Q
on off
!clk M3 C1 clk M7 C2
off on
M1 M5 Insensitive to clock
overlap as long as the
rise and fall times of
master transparent
the clock edges are
slave hold
clk sufficiently small
!clk master hold

slave transparent
B.Supmonchai
C2MOS FF 0-0 Overlap Case

M2 M6
0 M4 0 M8
QM
D Q
M3 C1 M7 C2
M1 M5
clk clk
!clk !clk

B.Supmonchai
Notes on C2MOS FF 0-0 Overlap Case

Does any new data sampled during the overlap window
propagate to Q (race)?
New data is sampled on QM, but cannot propagate to Q since
M7 is off (slave is in hold).
Any new data sampled on the falling clock edge is not seen at Q
For clocking on the left: at the end of the overlap period

!clk = 1 and both M7 and M8 turn off, putting the slave
in the hold mode
For the clocking on the right: at the end of the overlap
period clk = 1 and both M3 and M4 turn off, putting the
master in the hold mode (affects setup time as well)
The result: the FF is slower (slower tc-q time)
B.Supmonchai
C2MOS FF 1-1 Overlap Case

M2 M6
M4 M8
QM
D Q
1 M3 C1 1 M7 C2
M1 M5
clk clk
!clk !clk
1-1 overlap constraint: toverlap1-1 < thold

B.Supmonchai
Notes on C2MOS FF 1-1 Overlap Case

New data is sampled on QM, but cannot propagate to Q
since M8 is off (slave is in hold).
A bit more problematic than 0-0 overlap.
It must enforce a hold time on D, so that changing D which
reaches QM is not copied to Q when overlap time is over -
first clocking condition.
By imposing a hold time on D - that D must be stable during
clock overlap - overcome this problem as well
However, possible race can occur if the rise/fall times of
the clock are sufficiently slow.
Works correctly as long as the clock rise/fall times is smaller
than approximately five times the propagation delay of the
flipflop.
B.Supmonchai
C2MOS Transient Response

3
2.5 QM(3)
Q(3)
2
1.5
Q(0.1)
1
clk(0.1 ns)
0.5
clk(3 ns)
0
-0.5
0 2 4 6 8
Time (nsec)
For slow clocks, potential for a race condition exists

B.Supmonchai
True Single Phase Clocked (TSPC) Latches

Negative Latch Positive Latch
Q
In clk clk In
Q clk clk
hold when clk = 1 transparent when clk = 1

transparent when clk = 0 hold when clk = 0
Uses only a single clock

No clock overlap (skew) to worry about ; reduced clock load
B.Supmonchai
Embedding Logic in TSPC Latch
PUN A B
Q Q
In clk clk clk clk
A
PDN
B
A AND B
Logic can be embedded into latch (or FF)

Reduce delay overhead associated with the latch
B.Supmonchai
Notes on Embedding Logic in TSPC Latch

Set-up time increased, but overall performance
improved
The increase in the set-up time is typically smaller than the
delay of an AND gate.
For example, using minimum size devices set-up of AND
latch is 140 psec.
Using the conventional approach of AND gate followed by
latch has an effective set-up time of 600 psec.
Technique used extensively in the design of the EV4

DEC Alpha microprocessor and many other high
performance processors.

B.Supmonchai
TSPC ET FF
Master Slave
clk on clk on on on Q
D QM
off off clk off clk off
12 Transistors
master transparent 4 Clock loads
slave hold
master hold
clk slave transparent
Virtually all constraints removed - no clocks to overlap, no race
B.Supmonchai
Notes on TSPC ET FF
Warning! - similar to C2MOS, TSPC flipflops
malfunction when the slope of the clock is not
sufficiently steep.
Slow clock cause both the NMOS and PMOS
clocked transistors to be ON simultaneously,
resulting in undefined values of the states and race
conditions.
Clock slopes thus must be carefully engineered. If
necessary, local buffers must be introduced to ensure
the quality of the clock signal

B.Supmonchai
Simplified TSPC ET FF
I1 I2 I3
off
M3 clk on
M6 M9
Y1D
Q D
clk on X !D
D off M2 M5
clk off
on M8
M1 clk Moff
4 M7
on
9 Transistors*
4 Clock loads
I1 sample (transparent) *(11 if Q is needed)
I2 precharged
I3 hold
I1 hold
clk I2 evaluate
I3 sample (transparent)

B.Supmonchai
Notes on TSPC ET FF
On the positive edge of the clock, note that the node X
transitions to a low if D is high. Therefore, the input
must be kept stable until the value on node X before the
rising edge of the clock propagates to Y
Hold time of the register (less than 1 inverter delay since it
takes 1 inverter delay for the input to affect node X).
Propagation delay is essentially three inverters since

the value on node X must propagate to output Q
Set-up time is the time for node X to be valid one
inverter delay

B.Supmonchai
Sizing Issues in Simplified TSPC ET FF
3 clk
!Qmod
Transistor sizing
!Qorig
2
Original width
M4, M5 = 0.5m
1 M7, M8 = 2m
Qmod Qorig Modified width

0 M4, M5 = 1m
0 0.2 0.4 0.6 0.8 1
M7, M8 = 1m
Time (nsec)
Sizing is critical with improper sizing glitches may occur due

to race condition when the clock transitions from low to high
B.Supmonchai
Split-Output TSPC Latches

Positive Latch Negative Latch
Q A
In clk In clk
Q
A
transparent when clk = 1 hold when clk = 1

hold when clk = 0 transparent when clk = 0
When In = 0, A = VDD - VTn When In = 1, A = | VTp |

B.Supmonchai
Split-Output TSPC ET FF
8 Transistors*
2 Clock loads
*(10 if Q is needed)
clk A
D clk QM
Q
Which edge-triggered?
Downside is not all node voltages in the latch experience

full logic swing due to threshold drop.
E.g., for positive latch when D=0 and clk=1, A=Vdd-Vth (Also
limits the amount of Vdd scaling possible with this latch).
B.Supmonchai
Pulse-Triggered Flipflops
Another approach to design an edge-triggered
flipflop is to use pulse-triggered.
Master-Slave Flipflop Pulse-Triggered Flipflop
L1 L2 L
Data Data
D Q D Q D Q
Clk
Clk Clk Clk
Clk

B.Supmonchai
Pulsed FF (AMD-K6)
Pulse registers - a short pulse (glitch clock) is generated
locally from the rising (or falling) edge of the system
clock and is used as the clock input to the flipflop
0/Vdd ON/OFF
OFF
clk 0 1
P1ON X Vdd P3 Q 1/0
M3OFF M6OFF
ON ON
1/0
D M2ON/ P2 M5
1 OFF
1 0 1
M1ON M4
ON !clkd
0 OFF

B.Supmonchai
Notes on Pulsed FF
Race conditions are avoided by keeping the transparent
mode time very short (during the pulse only)
Reduce clock load but substantially increase complexity
in verification
The transparency period determines the hold time.
The window must be wide enough for the input data to
propagate to Q.
The set-up time can be NEGATIVE (if the transparency
window is longer than the delay from input to output).
This is attractive, as data can arrive at the register even after
the clock goes high, meaning that time can be borrowed from
the previous cycle.
B.Supmonchai
Sense Amp FF (StrongArm SA100)

Sense amplifier is a circuit that accept small swing input
signals and amplify them to full rail-to-rail signals
0 1
D 1
X 1 0 M9
M2 M5 M7
!S
Q
M1 M4
1 !R
!Q
M3 M6 M8
Y 1 1
0 M10
clk 0 1

B.Supmonchai
Notes on Sensed Amp FF

The key is transistor M4 (in the middle of Sensed amp);
it delays signals that pass through to the other side of its
terminal, making the change on the other side slower
When D = 1, Y changes after X due to the delay of M4. By the
time M6 reacts to the change at its terminal, it is already
turned off by the terminal voltage at M4 (a 0). Thus, M6
holds a 1.
M4 also provides DC-leakage path to ground for either
node X or Y in case that the inputs change their value
after the positive edge of CLK arrives.
Advantages are reduced clock load and that it can be
used as a receiver for reduced swing differential buses
Where does the differential signal enter?
B.Supmonchai
Flipflop Comparison Chart

Name Type #clk ld #tr tset-up thold tpFF
Mux Static 8 (clk-!clk) 20 3tpinv+tptx 0 tpinv+tptx
PowerPC Static 8 (clk-!clk) 16
2-phase Ps-Static 8 (clk1-clk2) 16
T-gate Dynamic 4 (clk-!clk) 8 tptx to1-1 2tpinv+tptx
C2MOS Dynamic 4 (clk-!clk) 8
TSPC Dynamic 4 (clk) 11 tpinv tpinv 3tpinv
S-O TSPC Dynamic 2 (clk) 10
AMD K6 Dynamic 5 (clk) 19
SA 100 SenseAmp 3 (clk) 20

B.Supmonchai
Choosing a Clocking Strategy

Choosing the right clocking scheme affects the
functionality, speed, and power of a circuit
Two-phase designs
+ robust and conceptually simple
- need to generate and route two clock signals
- have to design to accommodate possible skew between the
two clock signals
Single phase designs
+ only need to generate and route one clock signal
+ supported by most automated design methodologies
+ dont have to worry about skew between the two clocks
- have to have guaranteed slopes on the clock edges
B.Supmonchai
Non-Bistable Sequential Circuits

Previously, we have defined a circuit having two
stable states a bi-stable circuit
Other regenerative circuits, which are non-
bistable:
Monostable
Only one stable state -> Pulse generators, One-shot circuits
Astable
No stable states -> Oscillator, On-chip clock generator
Schmitt Trigger
A special regenerative circuit exhibiting hysteresis in VTC.

B.Supmonchai
Schmitt Trigger
Non-Bistable Sequential Circuits
Vou t V OH
In Out
2 important properties
V OL
Hysteresis
Fast Transition Time
at the output VM VM+ Vi n

B.Supmonchai
Noise Suppression using Schmitt Trigger
VIN VOUT
VM+
VM-
t0 t t0 + tp t
Example: Switch Debouncer

B.Supmonchai
CMOS Schmitt Trigger

VDD
Moves switching
threshold of the
first inverter
M2 M4
X
VIN VOUT
M1 M3 Low-to-High
reff = kM1/(kM2 + kM4)
High-to-Low
reff = (kM1 + kM3)/kM2
Adapting the ratio between PMOS and NMOS, depending upon the
direction of the transition results in a shift in switching threshold
B.Supmonchai
Schmitt Trigger Simulated VTC

M1 = 1 m/0.25 m, M2 = 3 m/0.25 m, M3 = 0.5 m/0.25 m
M4 = 1.5 m/0.25 m M4 = k x 0.5 m/0.25 m

2.5 2.5
2.0 2.0
1.5 VM1 1.5
Vout(V)
Vout(V)
1.0 VM2 1.0

k=1
k=3
k=2
0.5 0.5
k=4
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
Vin (V) Vin (V)
Voltage Transfer Characteristics Effect of varying the ratio of the

with hysteresis PMOS device M4
B.Supmonchai
CMOS Schmitt Trigger (2)
M4
How does the gate operate?
M6
M3
VIN VOUT
M2
M5
X
M1
Sketch VTC and find expression for VM- and VM+

B.Supmonchai
Review: Ring Oscillator

tp
Period: T = 2 x tp x N
Different Clock Duty-Cycles

and phases can be derived
using simple logic operations

B.Supmonchai
Voltage Controller Oscillator (VCO)

Oscillation frequency of a VCO is a function (typically
nonlinear) of a control voltage
Schmitt Trigger
VD D VDD
restores signal slopes
M6 M4
M2
In
M1
Iref Iref
Vcontr M3
M5 Current starved inverter
Delay of6a current starved inverter depends on the current

limit available to discharge the load capacitance of the gate
(nsec)
4
L
Vcontr M3
M5 Current starv
B.Supmonchai
Current-Starved Inverter Simulation

The device is in the
subthreshold region
6 when Vctrl is smaller
than VT, resulting in
L (nsec)
(nsec)
4 large variations of tp
as the drive current
is exponentially
tpHL
2
tpH
dependent on the
propagati
drive voltage
0.0
0.5 1.5 2.5 of control
Delay sensitive to
V co ntr (V)
Vctrl (V)
noise and variation
in Vctrl

B.Supmonchai
Differential Delay Element and VCO
- Vo2 Vo1 + v3
in1
v1
+ - in2
v2
v4
Vctrl
delay cell two stage VCO
- Inverting Inputs/Outputs Oscillator with even number

+ Non-Inverting Inputs/Outputs of stages can be implemented
Differential-type VCO has better immunity to common mode

noise (e.g., supply noise) but consume more power
B.Supmonchai
2-Stage VCO Simulation

3.0
V1 V2 V3 V4
2.5
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5 1.5 2.5 3.5
time (ns)
The In-Phase and Quadrature Phase are produced simultaneously

Ch7 Sequential

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Ch7 Sequential

Uploaded by

Copyright:

Available Formats

Chapter 7

Goals of This Chapter

Static versus Dynamic Realization

2102-545 Digital ICs Sequential Logic 2

Current State Next state

Positive Feedback Charge-Based

Static vs Dynamic Storage

2102-545 Digital ICs Sequential Logic 4

Latches versus Flipflops

2102-545 Digital ICs Sequential Logic 5

Review: The Regenerative Property

2102-545 Digital ICs Sequential Logic 6

Review: Bistable Circuits

Have to be able to change the stored value by making A

2102-545 Digital ICs Sequential Logic 7

2102-545 Digital ICs Sequential Logic 8

Review: Clocked D Latch

Latches versus Flipflops II

2102-545 Digital ICs Sequential Logic 10

Positive and Negative Latches

Out Out Out Out Out Out Out Out

2102-545 Digital ICs Sequential Logic 11

2102-545 Digital ICs Sequential Logic 12

tsu thold time

Out output output

Hold time, thold is the time that the data inputs

System Timing Constraints

Current State Next state

tcd: contamination delay = minimum delay

tcdreg + tcdlogic thold T tc-q + tplogic + tsu

2102-545 Digital ICs Sequential Logic 15

Notes on System Timing Constraints

Hold time becomes an issue when there is little logic

Building A (Static) Latch

Cutting the feedback loop Overpowering the feedback loop

2102-545 Digital ICs Sequential Logic 17

MUX Based Latches

Negative Latch Positive Latch

Q = clk & Q | !clk & D Q = !clk & Q | clk & D

TG MUX Based Latch Implementation

2102-545 Digital ICs Sequential Logic 19

PT MUX Based Latch Implementation

Reduced clock load, but !clk

2102-545 Digital ICs Sequential Logic 20

Latch Race Problem

clk Which value of B is stored?

T tc-q + tplogic + tsu

2102-545 Digital ICs Sequential Logic 21

Master Slave Based ET Flipflop

clk = 1 hold transparent Q

2102-545 Digital ICs Sequential Logic 22

master transparent master hold

2102-545 Digital ICs Sequential Logic 23

Propagation delay - time for QM to reach Q

Hold time - time D must be stable after rising edge of clk

Notes on MS ET Timing Properties

Set-up Time Simulation

Set-up Time Simulation II

Fails! the clock is enabled before the nodes on both sides

2102-545 Digital ICs Sequential Logic 27

Propagation Delay Simulation

propagation delay is measured from the 50% point

to switch the state of the master, T1 must be sized to overpower I2

Ideal clocks Non-Ideal clocks