VLSI DESIGN

Second Edition

Debaprasad Das

Oxford University Press 2015. All rights reserved.

 Chapter 1

Introduction to VLSI
Systems

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 Fig 1.1: Evolution of VLSI (major milestones)
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 Fig 1.2: Level of integration for Intel microprocessors
(Source: Intel Corporation)
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 Fig 1.3: Schematic view of IC technology
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 Fig 1.4: GajskiKuhn Y-chart
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 Fig 1.5: Hierarchical decomposition of an electronic
system
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 Fig 1.6: Hierarchical decomposition of CPU
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 Fig 1.7: VLSI design flow
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 Fig 1.8: Design iteration loop
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 Fig 1.9: Typical FPGA architecture
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 Fig 1.10: Gate array (GA) architecture: (a)
channelled; (b) channel-less; (c) structured
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 Fig 1.11: Standard cell-based architecture
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 Fig 1.12: An 8 4 ROM architecture
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 Fig 1.13: Block diagram of PAL architecture
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 Fig 1.14: Block diagram of PLA architecture
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 Fig 1.15: Integrated circuit development process
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 Fig 1.16: (a) Delay vs process technology; (b) delay vs power
supply voltage; (c) delay vs operating temperature
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 Fig 1.17: Delay vs chip area
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 Fig 1.18: Delay vs minimum feature size
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 Fig 1.19: Different VLSI design styles and different
aspects of VLSI design
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 Fig 1.20: VLSI design flow
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 Fig 1.21: (a) Block diagram; (b) test vectors; (c)
functional specification
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 Fig 1.22: Typical output of a function simulation
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 Fig 1.23: Design synthesis step
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 Fig 1.24: Schematic of CMOS inverter
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 Fig 1.25: Simulation results of the CMOS inverter
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 Fig 1.26: A typical IC layout
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 Fig 1.27: A circuit is partitioned into three sub-
circuits
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 Fig 1.28: A typical floorplan of integrated circuit
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 Fig 1.29:A typical placement of an integrated circuit
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 Fig 1.30: An example of routing in an integrated
circuit
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 Fig 1.31:(a) A graph without edge weights; (b) a
graph with edge weights
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 Fig 1.32: (a) A natural tree; (b) a tree that
represents a design hierarchy
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 Fig 1.33: (a) Spanning tree; (b) Steiner tree; (c)
rectilinear Steiner tree
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 Fig 1.34: Silicon-on-insulator process
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 Fig 1.35: Example of 3D integration: (a) several active layers
implementing logic, memory, and I/O; (b) die stack
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 Fig 1.36:(a) Tunnel diode and (b) double barrier
quantum well (DBQW) structure
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 Fig 1.37: (a) Biased RTD, (b) IV characteristics of RTD
and (c)(f) energy-band diagram of RTD
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 Fig 1.38: Schematic of a single electron transistor
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 Fig 1.39: (a) Conventional MOSFET and (b) organic FET
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