Distortion cancellation in

Time Interleaved ADC

By - Naga Thejus S M

Examiner: Prof. J Jacob Wikner Supervisor: Dr. Samer Medawar

 Presentation Outline
1. Introduction
2. Experimental set-up
3. Objective
4. Background Theory
5. Methodology
6. Validation
7. Conclusions and Future Work
 Introduction
Digital circuits vs Analog Circuits
Robust to noise.
Cheaper to implement.
Consumes less Bandwidth.
More Secure.
 Time Interleaved ADC
Consists of two or more
individual sub converters
Operates in a round robin
manner
 Time Interleaved ADC
Principle:
Sampling Period Sampling Freq.

Individual ADC Tsamp Fsamp

TI ADC Ts Fs

Ts = Tsamp/4
Fs = 4.Fsamp

Advantages:
Possible to achieve arbitrary sampling rates.
Reduces bill of materials cost, power, board size.
 Time Interleaved ADC
Disadvantages

Offset mismatch
Gain mismatch
Skew mismatch
Non-linear mismatches
Experimental Setup
Test bed schematic
Experimental Setup
Test bed set-up
 Experimental Setup
Device under test
TIADC12J4000 which is a 12 bit ADC by
Texas Instruments.
Capable of operating up to four Giga
samples per second.
Objective
A typical output of TI ADC under consideration in frequency domain.
 Objective
80 80
1 1
60 60

40 40

20 20
2

|Y(f)|

|Y(f)|
6 2 5 18
13 9 26 15 18 14
34 44 48
3 25 20 13 28 32 36 10 31 35
39
0 4 29 12
25 53 54
58 20 42 38 40
5 7 51 10 31 35 0 29 49 21 38 3 22 19 14 27 6
15
41 16
21 57 46 32 36 30
11 59 19 60 47
52
22 39 41 45
8 57 7
30
40 44 43
37 8
45
17 50 55 27 43 37 4 12 53
58
16 17
50 9
24 46 42 34 11 59 56 60
48 51 47
23
33 52
-20 33
49 28 56 23 -20 54 26 55
24
-40 -40

-60 -60
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000
Bins subconv 1 Bins subconv 2

80 100
1
60 1

50
40

20 8 7
4 19 23 2
|Y(f)|

|Y(f)|
4 29 12 3 7 15 19 23
14 6 2 0 37 16 17 24 9 42 38 3
46 5 26 15 14 43 35
21
33 8 25 16 20
17 13 9 54 50 28 32 36 40
41 45 25 21 20 34 30 48 22 56 51 27
55 60 47 31
10
0 41 38 40 30 11
18 29 12 58 57 13 44 11 18 6 39
37
45 53 54 42 36
28 5 55 60
26 22 56 10 31
51 27 43 35
39
33 49 53
59
52
49 58 24 46 34 59
48 52 47
-20 32
57 50 -50
44
-40

-60 -100
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000
Bins subconv 3 Bins subconv 4

The output of TI ADC contains a large number of harmonics which motivated

us to develop a calibration technique for the suppression of harmonics.
Background
j2 k j4 k j6 k
M M M
X ( k )= X 0 ( k )+ X 1 (k )e + X 2(k )e + X 3(k )e
 Background
Non linearity modelling
A non linear system could be modelled as a memoryless power series given as:

L
Y = ( A j x j)
j=0

Substituting for x=cos(2 ft+ o ) we get

1 2 3
Y = [( A 1 ( cos ( 2 ft + o )))+ ( A 2 (cos ( 2 ft + o )))+ ( A 3 (cos ( 2 ft + o )))]
Background

[ 1
Y ( A ' 1 (cos( 2 ft + o)))+ ( A2 (cos (4 ft+ 2 o )))
2
1
+ ( A3 (cos( 6 ft+ 3 o ))) .
4 ]
Dynamic nonlinear distortion causes the distortion terms to fall out of
phase with the fundamental

[ 1
Y (A ' 1 (cos(2 ft + o)))+ ( A2 (cos(4 ft+ 2 o+ d2 )))
2
1
+ ( A3(cos(6 ft+ 3 o+ d3)))
4 ]
 Background
Bandwidth divided into
number of equally spaced
frequency points
Frequency selection
performed as per to IEEE
1241
Background
 Methodology
Contains LTI Filters and non
linearity equation generator.
Could be designed for any
number of harmonics.
Methodology
Second Harmonic Filter Third Harmonic Filter
 Validation
original spectrum
100
1

50
2
3
|Y(f)|

-50

-100
0 1 2 3 4 5 6
Bins orig 4
x 10
Angle of the harmonics
4

3 3
Anglein radians

2 1

-1 2
0 1 2 3 4 5 6
Bins 4
x 10
Validation
Validation
Validation
Input signal at 780 MHz
Validation
Input signal at 850 MHz
Validation
Input signal at 990 MHz
Validation
Spread of harmonic suppression over the bandwidth
Validation
Spread of improvements in THD over the bandwidth
Validation
IMD improvements
Frequencies 880MHz - 890MHz 890MHz - 900MHz 898MHz - 909MHz 909MHz - 915MHz 910MHz - 920MHz

IMD & Harmonics IMPROVEMENTS in dB

2.f1 7.78 4.62 4.41 14.7 11.62

2.f2 7.68 7.78 5.38 13.49 11.387

3.f1 3 3.73 17.79 9.28 3.16

3.f2 2.8 3.77 12.01 6.49 3.83

f1 + f2 9.2 6.38 5.89 12.7 9.39

f1 - f2 7.22 6 8.17 6.48 5.02

2.f1 + f2 7.08 12.79 15.02 5.62 9.1

2.f2 + f1 8.01 12.81 20.09 4.46 7.27

2.f1 - f2 9.33 12.47 22.95 3.71 6.52

2.f2 - f1 11.07 10.78 6.9 3.42 4.22

 Conclusions
A post correction block to suppress
the harmonics was developed and
has been successfully validated.
This works on top of in chip
calibration.
Once modelled, this post
correction block works for any
type of input signal.
Efficient when compared to LUT
compensation methods
Future Work
Should be cross validated with a
state of the art ADC to realize the
full extent of the post correction
block.
It would be interesting to explore
the temperature and aging effects
on the post correction block.
THANK YOU