Reset Circuitry &

Watchdog Timers
Power management in ARM
The LPC2141/42/44/46/48 supports two
reduced power modes:
1)Idle mode :
2)Power-down mode:
 Power management in ARM
1)Idle mode :
execution of instructions is suspended until
either a reset or interrupt occurs
Peripheral functions continue operation
during Idle mode
May generate interrupts to cause the processor
to resume execution
Eliminates power used by the processor itself,
memory systems and related controllers, and
internal buses
Power management in ARM
2)Power-down mode.
oscillator is shut down and the chip receives no
internal clocks.
The processor state and registers, peripheral
registers, and internal SRAM values are
preserved throughout Power-down mode and
the logic levels of chip output pins remain
static.
normal operation resumed by either a reset or
certain specific interrupts
Power management in ARM
Register description: The Power Control function
contains two registers
(1)PCON Power Control Register: This register
contains control bits that enable the two reduced
power operating modes of the microcontroller.
(2) PCONP Power Control for Peripherals
Register: This register contains control bits that
enable and disable individual peripheral functions,
Allowing elimination of power consumption by
peripherals that are not needed.
PCON Power Control Register
The PCON register contains two bits. Writing a one to
the corresponding bit causes entry to either the
Power-down or Idle mode. If both bits are set, Power-
down mode is entered
Power control for peripherals (PCONP)

Power control for peripherals (PCONP)

Allows you to turn the internal peripherals of the
microcontroller (for example USB, analog to digital
converters, etc.) on or off. The advantage of doing this is
that you can save power by turning off any peripherals
that you aren't using, which can make a big difference if
your device is running off batteries or a similarly 'limited'
power source.
Power control for peripherals (PCONP)
Power control for peripherals (PCONP
Software Reliability
Embedded systems must be able to cope with
both hardware and software anomalies to be truly
robust.
In many cases, embedded devices operate in total
isolation and are not accessible to an operator.
Manually resetting a device in this scenario when
its software hangs is not possible.
In extreme cases, this can result in damaged
hardware or loss of life and incur significant cost
impact.
The Clementine
In 1994, a deep space probe, the Clementine, was launched to
make observations of the moon and a large asteroid (1620
Geographos).
After months of operation, a software exception caused a
control thruster to fire for 11 minutes, which depleted most of
the remaining fuel and caused the probe to rotate at 80 RPM.
Control was eventually regained, but it was too late to
successfully complete the mission.
 Watchdog Timers
A timing device such that it is set for a preset time interval
and an event must occur during that interval else the device
will generate the timeout signal on failure to get that event
in the watched time interval.
On that event, the watchdog timer is disabled to disable
generation of timeout or reset
Timeout may result in processor start a service routine or
start from beginning.
For those embedded systems that can't be
constantly watched by a human, watchdog timers
may be the solution.
 Watchdog Timers
While it is not possible to cope with all hardware and software
anomalies, the developer can employ the use of watchdog timers
to help mitigate the risks.
A watchdog timer is a hardware timing device that triggers a
system reset, or similar operation, after a designated amount of
time has elapsed.
A watchdog timer can be either a stand-alone hardware
component or built into the processor itself.
To avoid a reset, an application must periodically reset the
watchdog timer before this interval elapses. This is also known
as kicking the dog.
A watchdog timer (WDT) is an embedded timing device that
automatically prompts corrective action upon system
malfunction detection. If software hangs or , a WDT resets the
system microcontroller via a 16-bit count
 Watchdog timer application

An application in mobile phone is that

display is off in case no GUI interaction
takes place within a watched time interval.
The interval is usually set at 15 s, 20 s, 25 s,
30 s in mobile phone.
This saves power.
Watchdog Timer Features
Internally resets chip if not periodically reloaded.
Enabled by software but requires a hardware reset
or a watchdog reset/interrupt to be disabled.
Incorrect/Incomplete feed sequence cause
reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32-bit timer with internal pre-
scaler.(Minimum value is 0xFF).
Selectable time period from (TPCLK x 256 x 4) to
(TPCLK x 232 x 4) in multiples of TPCLK x 4.
Watchdog Timer
The watchdog should be used in the following manner:
Set the watchdog timer constant reload value in WDTC
register.
Setup mode in WDMOD register.
Start the watchdog by writing 0xAA followed by
0x55 to the WDFEED register.
Watchdog should be fed again before the watchdog
counter underflows to prevent reset/interrupt.
Watchdog timer :Register description
Watchdog timer :Register description
Watchdog timer :Register description

WDTOF The Watchdog Time-Out Flag is set when the

watchdog times out. This flag is cleared by software.
WDINT The Watchdog Interrupt Flag: is set when the
watchdog times out. This flag is cleared when any reset
occurs. Once the watchdog interrupt is serviced, it can be
disabled in the VIC or the watchdog interrupt request will
be generated indefinitely
Watchdog timer Constant register
The WDTC register determines the time-out value.
Every time a feed sequence occurs the WDTC content
is reloaded in to the watchdog timer.
Its a 32-bit register with 8 LSB set to 1 on reset.
Writing values below 0xFF will cause 0xFF to be loaded
to the WDTC. Thus the minimum time-out interval is
TPCLK 256 4.
Watchdog Feed register
Setting the WDEN bit in the WDMOD register is not
sufficient to enable the watchdog.
A valid feed sequence must first be completed
before the Watchdog is capable of generating an
interrupt/reset.
Once 0xAA is written to the WDFEED register the
next operation in the Watchdog register space
should be a WRITE (0x55) to the WDFFED register
otherwise the watchdog is triggered.
Watchdog Timer Value register(WDTV)
Watchdog Timer Value register (WDTV - 0xE000 000C)
The WDTV register is used to read the current value of watchdog
timer.
WDT
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Conclusion
Watchdog timers can add a great deal of reliability to embedded
systems if used properly.
To do so requires a good overall approach. Resetting the
watchdog timer must be part of the overall design.
Verify the operation integrity of the system, and use this as a
criteria for resetting the watchdog timer.
In addition to validating that the software does the right thing,
verify that it does so in the time expected.
Assume the software will experience a hardware malfunction or
software fault. Add enough debugging information to help debug
situation.
Reset Circuitry
 Reset Circuitry
A LOW on this pin resets the chip, causing I/O ports and
peripherals to take on their default states, and the processor to
begin execution at address 0x0000 0000.
XTAL/RTXC
Reset Circuitry
 Reset Circuitry(MCP 130T)
Precision monitoring of 3V, 3.3V and 5V systems
Active low RESET pin(assert the RESET signal
whenever the voltage on the VDD pin is below
the trip-point voltage.)
Internal pull-up resistor (5 k) for MCP130
Protection from brown-out conditions when the
supply voltage drops below a safe operating
level.
Voltage supervisory device designed to keep a
microcontroller in reset until the system voltage
has reached the proper level and stabilized
Memory
Memory
 Types of memory
MEMORY

PRIMARY MEMORY SECONDARY MEMORY

(INTERNAL MEMORY) (EXTERNAL MEMORY)

CPU
MAGNETIC MAGNETIC OPTICAL
ON CHIP TAPE DISK
REGISTER DISK
CACHE

RAM ROM

DRAM SRAM PROM EPROM EEPROM

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 Primary Memory
The storage type is temporary
It is volatile memory
Storage capacity is limited
It is part of CPU.
Used for storing a little volume of data at the
time of processing.
The semiconductor memory is employed as the
main memory (or primary memory).
It stores programs and data which are currently
needed by the CPU
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 Secondary memory
The magnetic memory is called as the secondary
memory (auxiliary memory).
The information which is needed by the CPU for
current processing is transferred from the
secondary memory to the main memory.
This is non-volatile memory, i.e., data is stored
permanently.
The secondary memory is used for bulk storage
(mass storage) of programs, data and other
information.

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 SRAM vs DRAM

SRAM is faster compared to DRAM

SRAM consumes less power than DRAM
SRAM uses more transistors per bit of memory
compared to DRAM
SRAM is more expensive than DRAM
Cheaper DRAM is used in main memory while SRAM
is commonly used in cache memory
DRAM Required Refresh cycle
DRAM Required EDC Circuit
 Types Of ROM

1. PROM - (Programmable Read Only

Memory)

2. EPROM - (Erasable Programmable Read

Only Memory)

3. EEPROM - (Electrically Erasable PROM)

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 PROM
This stands for Programmable Read Only Memory. It is a
semiconductor memory which can only have data written to it
once - the data written to it is permanent. These memories are
bought in a blank format and they are programmed using a
special PROM programmer. Typically a PROM will consist of an
array of fuse links some of which are "blown" during the
programming process to provide the required data pattern.
 EPROM
This is an Erasable
Programmable Read
Only Memory.
Exposing the silicon to
ultraviolet light. To
enable this to happen
there is a circular
window in the
package of the
EPROM to enable the
light to reach the
silicon of the chip.
When the PROM is in
use, this window is
normally covered by a
label, specially when
the data may need to
be reserved for an
extended period
 EEPROM
Electrically erasable programable read-only memory (EEPROM) is
Data can be written to it and it can be erased using an electrical
voltage. , but allows its entire contents to be electrically erased or
rewritten, This is typically applied to an erase pin on the chip. Like
other types of PROM, EEPROM retains the contents of the memory
even when the power is turned off. Also like other types of ROM,
EEPROM is not as fast as RAM.

EEROM FLASH
 Flash memory:
In essence it uses the same method of programming as
the standard EPROM and the erasure method of the
E2PROM.
Flash memory can be seen in many forms today
including flash memory USB memory sticks, digital
camera memory cards in the form of compact flash or
secure digital, SD memory.
EEPROMs are changed 1byte at a time, which makes
them versatile but slow.
Flash memory, a type of EEPROM that uses in-circuit
wiring to erase by applying an electrical field to the
entire chip or to predetermined sections of the chip
called blocks.
 Memory hierarchy
Good system design is a balance of many trade-offs to
achieve the overall system performance and costgoals. An
important part of this decision process is the memory
provision:
Types of memory, for example ROM, Flash, DRAM,
SRAM, disk based storage
Size - capacity and silicon area
Acess speed - core clock cycles required to read
or write a location
Architecture - Harvard (separate instruction and
data memories) or Von Neumann (unified memory
(AMBA) Bus System
AMBA defines a multilevel busing system, with a system
bus and a lower-level peripheral bus. These include two
system buses
AMBA High-Speed Bus (AHB)
Advanced Peripheral Bus (APB)
MEMORY MAP
Peripheral Memory map

AHB section is 128 x 16 kB blocks (totaling 2

MB).
APB section is 128 x 16 kB blocks (totaling
2MB).
Both the AHB and APB peripheral areas are 2
megabyte spaces which are divided up into 128
peripherals. Each peripheral space is 16 kilobytes in
size. This allows simplifying the address decoding for
each peripheral.
All peripheral register addresses are word aligned (to
32-bit boundaries) regardless of their size.
SRAM 8 ,16,32 & 64KB
Memory mapped I/O & I/O mapped I/O
Memory mapped I/O & I/O mapped I/O
Memory mapped I/O Isolated I/O
Devices and memory share Separate address
an address space
spaces
I/O looks just like memory
read/write Need I/O or
No special commands for memory select lines
I/O Special commands
Large selection of memory for I/O
access commands available
Limited set