L

O
C
A
L
I
Analysis of aLet theirnumber
large be a typical
of computer program has
typical program T
with lots of loops and subroutine calls
shown that references to memory at any given Y
encountered frequently. When loop is
interval of time tendthe
executed, toCPU
be confined
repeatedlywithin a set
refers to few OF
localized areas in memory.
of instructions This phenomenon
in memory that constitutesis R
known as thetheproperty LOCALITY
loop. Everyoftime OF
a subroutine is REFERENCE
called,
E
Its set of instructions are fetched from
the memory. thus loops and subroutines F
tend to localize the reference to the memory. E
R
E
N
C
E
Let's- take a look at the following pseudo-code to see
why locality of reference works

Output to screen << Enter a number between 1 and 100 >>

Read input from user
Put value from user in variable X
Put value 100 in variable Y
Put value 1 in variable Z
Loop Y number of time
Divide Z by X
If the remainder of the division = 0
then output << Z is a multiple of X >>
Add 1 to Z
Return to loop
End
 SRAM
To cache (static
is toRAM) does not use
set something capacitors
aside, to
or to store
forstore ones anduse.
anticipated zeroes.
MassInstead,
storage SRAM
is much usesslower
a
special circuit called a flip-flop.
than RAM, and RAM is much slower than the
The advantages of SRAM are that it is fast and it
CPU.not
does Caching, in PC
have to be terms,because
refreshed, is the holding of a
it uses the
flip-flop
recently circuit
used to store each
or frequently bit.code
used A flip-flop
or data in
circuit memory
a special will toggle on or off
location forand retain
rapid its
retrieval.
position, whereas a standard memory circuit
Speed is everything
requires when it comes
constant refreshing to computers.
to maintain an on
The high-speed memory state.chip generally used for
The main disadvantage
caching isofcalled
SRAM is that it is
S R Athan
more expensive M DRAM.
When CPU refers to the cache and finds the word
in cache, it is said to produce a HIT.
If word is not found it is known as MISS.

The performance of cache memory is frequently measured

in terms of a quantity known as HIT RATIO.

Total No. of HITS

HIT RATIO=
Total No. of CPU Reference (HIT+MISS)
•Each•word
Storesofboth
cache can store
address and two or
Thewords
•Divides
more transformation
address
of of
memory 15 ofinto
bits
under data
same
content of the memory word.
from
tag
indexfieldmain
and
address. memory
index
Each field.
data to cache
word is
This
memory
permits
is with
any
referred
location
to as a
Tag
storedis matched
together
in cache to find
its
to store process. a
tag and
any word from
Mapping
data word.
number of tag-data items in one
the memory.
word of cache is said to form a set.
•FIFO (first in first out):
Selects for replacement the item that has been in set
for longest time.

•Random Replacement:
Chooses one tag-data item for replacement at
random.

•LRU (Least Recently Used):

Chooses one tag-data item for replacement that has
been least recently used by CPU.
 W
R
In this method both main memory and I
cache is updated in parallel. T
It ensures that an I/O device
communicating through DMA would I
receive the most recent updated data. N
G
I
N
T
O
 In this Method only cache location is
updated with every request. C
Main Memory is updated only when A
word is to be displaced from cache.
C
H
E
Cache Initialization:
Cache is initialized when power is applied to
computer or when main memory is loaded with
complete set of programs.

After initialization, cache is considered to be

empty, but in effect it contains some invalid
data. Here comes the concept of VALID BIT.

Valid bit: it indicates if the word contains

valid data.
If ‘0’ new word automatically replaces the
previous invalid data.
If ‘1’, Word is preloaded in the memory.