Chapter 10

Computer Design Basics

Henry Hexmoor 1
 10-1

Computer Specification
Instruction Set Architecture (ISA) - the
specification of a computer's appearance to a
programmer at its lowest level
Computer Architecture - a high-level
description of the hardware implementing the
computer derived from the ISA
The architecture usually includes additional
specifications such as speed, cost, and
reliability.

Henry Hexmoor 2
 Introduction (continued)

Simple computer architecture decomposed

into:
Datapath for performing operations
Control unit for controlling datapath operations
A datapath is specified by:
A set of registers
The microoperations performed on the data
stored in the registers
A control interface

Henry Hexmoor 3
 Datapaths
10-2
Guiding principles for basic datapaths:
The set of registers
Collection of individual registers
A set of registers with common access resources called a
register file
A combination of the above
Microoperation implementation
One or more shared resources for implementing
microoperations
Buses - shared transfer paths
Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations
Shifter - shared resource for implementing shift
microoperations
Henry Hexmoor 4
 Datapath Example
Figure 10-1
Four parallel-load Load enable
Write A address
A select B select
B address
D data n
registers (R0-R3) Load R0 2 2
Two mux-based n n

register selectors Load

R1
0

Register destination n 1
2
MUX
n
3
decoder Load
0
1
MUX
R2 2
Mux B for external n n
3

constant input Load R3

n n

Buses A and B with external

0 1 2 3 n Register file
Decoder
A data B data
D address
address and data outputs 2 Constant in n
Destination select
n

n 1 0

ALU and Shifter with

MB select
MUX B Address
Bus A n
Bus B n Out
Data
Mux F for output select G select
A B
H select
n Out

4 A B 2 B

Mux D for external data input S2:0 || Cin S

V Arithmetic/logic 0 IR Shifter IL 0
C unit (ALU)

Logic for generating status bits

G H
N n
n
Z Zero Detect

V, C, N, Z MF select
0
MUX F
1
Function unit
F
n n Data In
0 1
Henry Hexmoor n
5 MD select
Bus D
MUX D
 Datapath Example: Performing a
Microoperation
Load enable A select B select

Microoperation: R0 R1 + R2 Write
D data n
A address B address

Apply 01 to A select to place Load R0 2 2

contents of R1 onto Bus A n n

Apply 10 to B select to place Load

R1
0
contents of R2 onto B data and n 1
MUX
2
apply 0 to MB select to place n
0 3

B data on Bus B Load

R2
1
2
MUX

Apply 0010 to G select to perform n n

3

addition G = Bus A + Bus B Load R3

n n
Apply 0 to MF select and 0 to MD 0 1 2 3
Decoder
n Register file
A data B data
select to place the value of G onto 2
D address
Constant in n n

BUS D Destination select

MB select
n 1 0

Apply 00 to Destination select to

MUX B Address
Bus A n
Bus B n Out
Data
enable the Load input to R0 G select
A B
H select
n
B
Out

4 A B 2
Apply 1 to Load Enable to force the V
S2:0 || Cin
Arithmetic/logic 0
S
IR Shifter IL 0
unit (ALU)
Load input to R0 to 1 so that R0 is N
C
G
n
H
n
loaded on the clock pulse (not shown) Z Zero Detect
0 1
MF select MUX F Function unit
The overall microoperation requires F
n n Data In

1 clock
Henry cycle
Hexmoor 6 MD select
Bus D
0 1
MUX D
n
 Arithmetic Logic Unit (ALU)

In this and the next section, we deal with detailed design

of typical ALUs and shifters
Decompose the ALU into:
An arithmetic circuit
A logic circuit
A selector to pick between the two circuits
Arithmetic circuit design
Decompose the arithmetic circuit into:
An n-bit parallel adder
A block of logic that selects four choices for the B input to the
adder
See next slide for diagram

Henry Hexmoor 7
 Arithmetic Circuit Design
Figure 10-3 and Table 10-1 and table 10-2
(pages
There are only four functions of B 435,
to select438)
as Y in G = A + Y:
Cin = 0 Cin = 1
All 0s G =A G=A+ 1
B G =A+ B G=A+ B +1
B G =A+ B G = A + B + 1 Subtraction
All 1s G=A 1 G=A

Cin

n
A X

n n-bit n G = X Y + Cin
B parallel
n adder
B input Y
S0 logic
S1

Henry Hexmoor 8
Cout
 Logic Circuit

The text gives a circuit implemented using a multiplexer

plus gates implementing: AND, OR, XOR and NOT
Here we custom design a circuit for bit Gi by beginning
with a truth table organized as logic operation K-map
and assigning (S1, S0) codes to AND, OR, etc.
Gi = S0 Ai Bi + S1 Ai Bi S1S0 AND OR XOR NOT
+ S0 Ai Bi + S1 S0 Ai
AiBi 0 0 0 1 11 10
Gate input count for
MUX solution > 29 00 0 0 0 1
Gate input count for 01 0 1 1 1
above circuit < 20
11 1 1 0 0
Custom design better
10 0 1 1 0
Henry Hexmoor 9
 Arithmetic Logic Unit (ALU)

The custom circuit has interchanged the (S1,S0) codes for XOR and NOT
compared to the MUX circuit. To preserve compatibility with the text,
we use the MUX solution.
Next, use the arithmetic circuit, the logic circuit, and a 2-way
multiplexer to form the ALU. See the next slide for the bit slice diagram.
The input connections to the arithmetic circuit and logic circuit have
been been assigned to prepare for seamless addition of the shifter,
keeping the selection codes for the combined ALU and the shifter at 4
bits:
Carry-in Ci and Carry-out Ci+1 go between bits
Ai and Bi are connected to both units
A new signal S2 performs the arithmetic/logic selection
The select signal entering the LSB of the arithmetic circuit, Cin, is
connected to the least significant selection input for the logic circuit,
S0 .
Henry Hexmoor 10
 Arithmetic Logic Unit (ALU)
Figure 10-7
Ci Ci Ci +1

Ai Ai
One stage of
Bi B i arithmetic
circuit 2-to-1
S0 S0
0 MUX
S1 S1
Gi

1
Ai S
B i One stage of
logic circuit
C in S0
S1

S2
The next most significant select signals, S0 for the arithmetic circuit and
S1 for the logic circuit, are wired together, completing the two select
signals for the logic circuit.
The remaining S1 completes the three select signals for the arithmetic
circuit.
Henry Hexmoor 11
 Combinational Shifter Parameters
10-4
Direction: Left, Right
Number of positions with examples:
Single bit:
1 position
0 and 1 positions
Multiple bit:
1 to n 1 positions
0 to n 1 positions
Filling of vacant positions
Many options depending on instruction set
Here, will provide input lines or zero fill

Henry Hexmoor 12
 4-Bit Basic Left/Right Shifter (Figure 10-8)

B3 B2 B1 B0
Serial
output L

Serial
output R
IR IL
0 1 2 M 0 1 2 M 0 1 2M 0 1 2M
S U S U S U S U
X X X X

2
S
H3 H2 H1 H0
Serial Inputs: Shift Functions:
IR for right shift (S1, S0) = 00 Pass B unchanged
IL for left shift 01 Right shift
Serial Outputs 10 Left shift
R for right shift (Same as MSB input) 11 Unused
L for left shift (Same as LSB input)
Henry Hexmoor 13
 Barrel Shifter
(Figure 10-9)
D3 D2 D1 D0

S0
S1
3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0
M M M M
U U U U
X X X X

Y3 Y2 Y1 Y0
A rotate is a shift in which the bits shifted out are inserted into the
positions vacated
The circuit rotates its contents left from 0 to 3 positions depending on S:
S = 00 position unchanged S = 10 rotate left by 2 positions
S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions
See Table 10-3 in text for details (page 440)
Henry Hexmoor 14
 Barrel Shifter (continued)

Large barrel shifters can be constructed by

using:
1. Layers of multiplexers - Example 64-bit:
Layer 1 shifts by 0, 16, 32, 48
Layer 2 shifts by 0, 4, 8, 12
Layer 3 shifts by 0, 1, 2, 3
See example in section 12-2 of the text
2. 2 dimensional array circuits designed at the
electronic level

Henry Hexmoor 15
 Datapath Representation
10-5
Here we move up one level in the n

hierarchy from that datapath Write

D data
m
The registers, and the D address
2mx n
multiplexer, decoder, and enable Register file
m m
hardware for accessing them A address B address

become a register file A data B data

Constant in n
A register file is an array of fast n
n

1 0
MB select MUX B
registers
Bus A n
Address out
The ALU, shifter, Mux F and Bus B n
Data out
status hardware become a 4 A B
FS
function unit V
The remaining muxes and buses C Function
unit
N
which handle data transfers are Z
F
at the new level of the hierarchy n
n Data in

MD select 0 1
Henry Hexmoor 16 MUX D
 Datapath Representation (continued)
n

D data
In the register file: m
Write
D address
Multiplexer select inputs become 2mx n
Register file
A address and B address m m
A address B address
Decoder input becomes D A data B data
address Constant in n
n
Multiplexer outputs become A n
1 0
data and B data MB select
MUX B
Input data to the registers Bus A n
Address out
Bus B n
becomes D data Data out

Load enable becomes write FS

4 A B

The register file now appears like V

Function
C
unit
a memory based on clocked flip- N
flops (the clock is not shown) Z
F
n
The function unit labeling is quite n Data in

straightforward except for FS MD select 0 1

MUX D

Henry Hexmoor 17
 Definition of Function Unit Select (FS) Codes
G Select, H Select, and MF
in T (Table 10-4, page 443))
of FS Codes

MF G H
FS(3:0) Select Select(3:0) Select(3:0) Microoperation

0000 0 0000 XX F A Boolean

0001 0 0001 XX F A + 1
0010 0 0010 XX F A + B Equations:
0011 0 0011 XX F A + B + 1
0100 0 0100 XX F A + B
MF = F3 F2
0101 0 0101 XX F A + B + 1 Gi = Fi
0110 0 0110 XX F A - 1
0111 0 0111 XX F A Hi = Fi
1000 0 1 X00 XX F A B
1001 0 1 X01 XX F A B
1010 0 1 X10 XX F A B
1011 0 1 X11 XX F A
1100 1 XXXX 00 F B
1101 1 XXXX 01 F sr B
1110 1 XXXX 10 F sl B

Henry Hexmoor 18
 The Control Word

The datapath has many control inputs

The signals driving these inputs can be
defined and organized into a control word
To execute a microinstruction, we apply
control word values for a clock cycle. For
most microoperations, the positive edge of
the clock cycle is needed to perform the
register load
The datapath control word format and the
field definitions are shown on the next slide
Henry Hexmoor 19
 The Control Word Fields

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA AA BA M FS MR
B D W

Control word
Fields
DA D Address (destination)
AA A Address
BA B Address (source for MUXB
MB Mux B (constant/source
FS Function Select
MD Mux D
RW Register Write
The connections to datapath are shown in the next slide
Henry Hexmoor 20
 Control Word Block Diagram (Figure 10-11)
n

RW 0 Write D data

15
DA 14 D address
13 8x n
Register file
12 9
AA 11 A address B address 8 BA
10 7
A data B data
n n

n
Constant in

1 0
MB 6 MUX B
Bus A n
Address out
Bus B n
Data out

A B

V 5
C Function 4 FS
N unit 3
Z 2

n
n Data in

0 1
MD 1 MUX D
Bus D

Henry Hexmoor 21
 Control Word Encoding
Encoding of Control W Table 10-5
DA, AA, BA MB FS MD RW

Function Code Function Code Function Code Function Code Function Code

R0 000 Register 0 F A 0000 Function 0 No write 0

R1 001 Constant 1 F A + 1 0001 Data In 1 Write 1
R2 010 F A + B 0010
R3 011 F A + B + 1 0011
R4 100 F A + B 0100
R5 101 F A + B + 1 0101
R6 110 F A - 1 0110
R7 111 F A 0111
F A B 1000
F A B 1001
F A B 1010
F A 1011
F B 1100
F sr B 1101
F sl B 1110

Henry Hexmoor 22
 Microoperations for the Datapath -
Symbolic Representation
Micro- Table 10-6
operation DA AA BA MB FS MD RW

R1R2 R3 R1 R2 R3 Register F = A +B + 1 Function Write

R 4 sl R6 R4 R6 Register F = sl B Function Write
R7R7 + 1 R7 R7 Re gister F = A +1 Function Write
R1R0 + 2 R1 R0 Con stant F = A +B Func tion Write
Data out R 3 R3 Register No Wr ite
R 4 D ata in R4 Data in Write
R 5 0 R5 R0 R 0 Register F = A B Function Write

Henry Hexmoor 23
 Microoperations for the Datapath - Binary
m
RepresentationBinary Co
Microoperations from Ta o

Micro-
Table 10-7
operation DA AA BA MB FS MD RW

R1R2 R3 001 010 011 0 0101 0 1

R 4 sl R6 100 XXX 110 0 1110 0 1
R7R7 + 1 111 111 XXX 0 0001 0 1
R1R0 + 2 001 000 XXX 1 0010 0 1
Data out R 3 XXX XXX 011 0 XXXX X 0
R 4 D ata in 100 XXX XXX X XXXX 1 1
R50 101 000 000 0 1010 0 1

Results of simulation of the above on the

next slide

Henry Hexmoor 24
 Datapath Simulation
Figure 10-12
clock 1 2 3 4 5 6 7 8
DA 1 4 7 1 0 4 5
AA 2 0 7 0
BA 3 6 0 3 0
FS 5 14 1 2 0 10
Constant_in X 2 X
MB
Address_out 2 0 7 0
Data_out 3 6 0 2 3 0
Data_in 18 18
MD
RW
reg0 0
reg1 1 255 2
reg2 2
reg3 3
reg4 4 12 18
reg5 5 0
reg6 6
reg7 7 8
Henry Hexmoor Status_bits 2 0 25 0 1 X
 Instruction Set Architecture (ISA) for Simple
Computer (SC)
10-7
A programmable system uses a sequence of instructions to control its
operation
An typical instruction specifies:
Operation to be performed
Operands to use, and
Where to place the result, or
Which instruction to execute next
Instructions are stored in RAM or ROM as a program
The addresses for instructions in a computer are provided by a program
counter (PC) that can
Count up
Load a new address based on an instruction and, optionally, status
information

Henry Hexmoor 26
 Instruction Set Architecture (ISA) (continued)

The PC and associated control logic are part of the

Control Unit
Executing an instruction - activating the necessary
sequence of operations specified by the instruction
Execution is controlled by the control unit and
performed:
In the datapath
In the control unit
In external hardware such as memory or input/output

Henry Hexmoor 27
 ISA: Storage Resources
Figure 10-13
The storage resources are "visible" to the programmer at the lowest
software level (typically, machine or assembly language)
Storage resources
for the SC => Program counter
(PC)
Separate instruction and Instruction
data memories imply memory
"Harvard architecture" 215 x 16
Done to permit use of
single clock cycle per Register file
8 x 16
instruction implementation
Due to use of "cache" in
modern computer
Data
architectures, is a fairly memory
realistic model 215 x 16

Henry Hexmoor 28
 ISA: Instruction Format

A instruction consists of a bit vector

The fields of an instruction are subvectors
representing specific functions and having specific
binary codes defined
The format of an instruction defines the subvectors
and their function
An ISA usually contains multiple formats
The SC ISA contains the three formats presented on
the next slide

Henry Hexmoor 29
 ISA: Instruction Format
Figure 10-14
15 9 8 6 5 3 2 0
Destination Source reg- Source reg-
Opcode register (DR) ister A (SA) ister B (SB)
(a) Register
15 9 8 6 5 3 2 0
Destination Source reg-
Opcode register (DR) ister A (SA) Operand (OP)

(b) Immediate
15 9 8 6 5 3 2 0
Address (AD) Source reg- Address (AD)
Opcode (Left) ister A (SA) (Right)

(c) Jump and Branch

The three formats are: Register, Immediate, and Jump and Branch
All formats contain an Opcode field in bits 9 through 15.
The Opcode specifies the operation to be performed
More details on each format are provided on the next three slides

Henry Hexmoor 30
 ISA: Instruction Format (continued)
15 9 8 6 5 3 2 0

Destination Source reg- Source reg-

Opcode register (DR) ister A (SA) ister B (SB)

(a) Register
This format supports instructions represented by:
R1 R2 + R3
R1 sl R2
There are three 3-bit register fields:
DR - specifies destination register (R1 in the examples)
SA - specifies the A source register (R2 in the first
example)
SB - specifies the B source register (R3 in the first
example and R2 in the second example)

Henry Hexmoor 31
 ISA: Instruction Format (continued)
15 9 8 6 5 3 2 0

Destination Source reg-

Opcode register (DR) ister A (SA) Operand (OP)

(b) Immediate

This format supports instructions described by:

R1 R2 + 3
The B Source Register field is replaced by an Operand field OP
which specifies a constant.
The Operand:
3-bit constant
Values from 0 to 7
The constant:
Zero-fill (on the left of) the Operand to form 16-bit constant
16-bit representation for values 0 through 7

Henry Hexmoor 32
 ISA: Instruction Format (continued)
15 9 8 6 5 3 2 0

Address (AD) Source reg- Address (AD)

Opcode (Left) ister A (SA) (Right)

(c) Jump and Branch

This instruction supports changes in the sequence of instruction execution by
adding an extended, 6-bit, signed 2s-complement address offset to the PC value
The 6-bit Address (AD) field replaces the DR and SB fields
Example: Suppose that a jump is specified by the Opcode and the PC
contains 45 (00101101) and Address contains 12 (110100). Then the new
PC value will be:
00101101 + (1110100) = 00100001 (45 + ( 12) = 33)
The SA field is retained to permit jumps and branches on N or Z based on the
contents of Source register A

Henry Hexmoor 33
 ISA: Instruction Specifications

The specifications provide:

The name of the instruction
The instruction's opcode
A shorthand name for the opcode called a mnemonic
A specification for the instruction format
A register transfer description of the instruction, and
A listing of the status bits that are meaningful during an
instruction's execution (not used in the architectures defined
in this chapter)

Henry Hexmoor 34
 ISA: Instruction Specifications (continued)

Instruction Specifications for the SimpleComputer - Part 1

St atus
Instruction Opcode Mnemonic Format Description Bits

Move A 0000000 MOVA RD ,RA R [DR] R[SA ] N, Z

Increment 0000001 INC R D,RA R[DR] R [SA] +1 N, Z
Add 0000010 ADD R D,RA,RB R [DR] R[SA ] + R[ SB] N, Z
Subtract 0000101 SUB R D,RA,RB R [DR] R[SA ] - R [SB] N, Z
D ecrement 0000110 DEC R D,RA R[DR] R[SA ] -1 N, Z
AND 0001000 AND R D,RA,RB R [DR] R[SA ] R[SB ] N, Z
OR 0001001 OR RD,RA,RB R[DR] R[SA] R[SB] N, Z
Exclusive OR 0001010 XOR RD,RA,RB R[DR] R[SA] R[SB] N, Z
NO T 0001011 NO T R D,RA R[DR] R[SA ] N, Z

Henry Hexmoor 35
 ISA: Instruction Specifications (continued)

Instruction Specifications for the Simple Computer - Part 2

St atus
Instr uction Opcode Mnemonic Format Description Bits

Move B 0001100 MOVB RD,RB R[DR] R[SB]

Shift Right 0001101 SHR RD,RB R[DR] sr R[SB]
Shift Left 0001110 SHL RD,RB R[DR] sl R[SB]
Load Immediate 1001100 LDI RD, OP R[DR] zf OP
Add Immediate 1000010 ADI RD,RA,OP R[DR] R[SA] + zf OP
Load 0010000 LD RD,RA R[DR] M[SA]
Store 0100000 ST RA,RB M[SA] R[SB]
Branch on Zero 1100000 BRZ RA,AD if (R[SA] = 0) PC PC + se A D
Branch on Negative 1100001 BRN RA,AD if (R[SA] < 0) PC PC + se A D
Jump 1110000 JMP RA PC R[SA ]

Henry Hexmoor 36
 ISA:Example Instructions and Data in
Memory
Memory Repr esentation of Instructions and Data

Deciimal Decimal
Address Memory Contents Opcode Other Fields Operation

25 0000101 001 010 011 5 (Subtract) DR:1, SA:2, SB:3 R1 R2 - R3

35 0100000 000 100 101 32 (Store ) SA:4, SB:5 M[R4] R5

45 1000010 010 111 011 66 (Add DR: 2, SA:7, OP :3 R2 R7 +3

Immediate)

55 1100000 101 110 100 96 (Branch AD: 44, SA:6 If R6 = 0,

on Zero) PC PC - 20

70 00000000011000000 Data = 192. Aft er execution of instruction in 35,

Data = 80.

Henry Hexmoor 37
 Single-Cycle Hardwired Control
10-8
Based on the ISA defined, design a computer architecture
to support the ISA
The architecture is to fetch and execute each instruction in
a single clock cycle
The datapath from Figure 10-11 will be used
The control unit will be defined as a part of the design
The block diagram is shown on the next slide

Henry Hexmoor 38
 IR(8:6) || IR(2:0)
V Extend
C Branch PC
N Control
Z

P JB Address
LBC Instruction
memory RW D
Instruction DA Register
AA file
A B BA
Zero fill
IR(2:0) Constant
in
Instruction decoder
1 0
MUX B MB
Address out
Bus A Bus B
Data out
MW
D B A M F M R M P J B
A A A B S D WW L B C A B Data in Address
FS
CONTROL
V Data
C Function memory
unit
N
Data out
Figure 10-15 Z
F

Data in

0 1
MD MUX D
Henry Hexmoor Bus D 39
DATAPATH
 The Control Unit

The Data Memory has been attached to the Address Out

and Data Out and Data In lines of the Datapath.
The MW input to the Data Memory is the Memory Write
signal from the Control Unit.
For convenience, the Instruction Memory, which is not
usually a part of the Control Unit is shown within it.
The Instruction Memory address input is provided by the
PC and its instruction output feeds the Instruction Decoder.
Zero-filled IR(2:0) becomes Constant In
Extended IR(8:6) || IR(2:0) and Bus A are address inputs to
the PC.
The PC is controlled by Branch Control logic
Henry Hexmoor 40
 PC Function (continued)

Branch Control determines the PC transfers based on five of

its inputs defined as follows:
N,Z negative and zero status bits
PL load enable for the PC
JB Jump/Branch select: If JB = 1, Jump, else Branch
BC Branch Condition select: If BC = 1, branch for N = 1, else
branch for Z = 1.
The above is summarize by the following table:
PC Operation PL JB BC
Count Up 0 X X
Jump 1 1 X
Branch on Negative (else Count Up) 1 0 1
Branch on Zero (else Count Up) 1 0 0

Henry Hexmoor 41
 Instruction Decoder

The combinational instruction decoder converts the instruction into the

signals necessary to control all parts of the computer during the single
cycle execution
The input is the 16-bit Instruction
The outputs are control signals:
Register file addresses DA, AA, and BA,
Function Unit Select FS
Multiplexer Select Controls MB and MD,
Register file and Data Memory Write Controls RW and MW, and
PC Controls PL, JB, and BC
The register file outputs are simply pass-through signals:
DA = DR, AA = SA, and BA = SB
Determination of the remaining signals is more complex.

Henry Hexmoor 42
 Instruction Decoder (continued)

The remaining control signals do not depend on the addresses, so must be a

function of IR(13:9)
Formulation requires examining relationships between the outputs and the
opcodes
Observe that for other than branches and jumps, FS = IR(12:9)
This implies that the other control signals should depend as much as
possible on IR(15:13) (which actually were assigned with decoding in
mind!)
To make some sense of this, we divide instructions into types as shown in
the table on the next page

Henry Hexmoor 43
 Instruction Decoder (continued)

Truth Table for Instruction Decoder Logic

Instruction Bits Control Wo rd Bits

Instruction Function Type 15 14 13 9 MB MD RW MW PL JB BC

Function unit operations using 0 0 0 X 0 0 1 0 0 X X

registers
Memory read 0 0 1 X 0 1 1 0 0 X X
Memory write 0 1 0 X 0 X 0 1 0 X X
Function unit operations using 1 0 0 X 1 0 1 0 0 X X
register and constant
Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0
Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 0 1
Unconditional Jump 1 1 1 X X X 0 0 1 1 X

Henry Hexmoor 44
 Instruction Decoder (continued)

The types are based on the blocks controlled and the seven signals to be
generated; types can be divided into two groups:
Datapath and Memory Control (First 4 types)
PC Control (Last 3 types)
In Datapath and Memory Control blocks controlled are considered:
Mux B (1st and 4th types)
Memory and Mux D (2nd and 3rd types)
By assigning codes with no or only one 1 for these, implementation of MB,
MD, RW and MW are simplified.
In Control Unit more of a bit setting approach was used:
Bit 15 = Bit 14 = 1 were assigned to generate PL
Bit 13 values were assigned to generate JB.
Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To
force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL.
Also, useful bit correlations between values in the two groups were
exploited in assigning the codes.
Henry Hexmoor 45
 Instruction Decoder (continued)

The end result by use of the types, careful assignment of

codes, and use of don't cares, yields very simple logic:
Instruction
This completes the Opcode DR SA SB
design of most of the 15 14 13 12 11 10 9 86 53 20

essential parts of
the single-cycle
simple computer

1917 1614 1311 10 96 5 4 3 2 1 0

DA AA BA MB FS MD RW MW PL JB BC
Henry Hexmoor 46
Control word