Chapter 9

Memory Organization

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 Chapter Outline
Hierarchical Memory Systems
Cache Memory
Virtual Memory
Pentium/Windows Memory System

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Memory Hierarchy

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 Associative Memory
Data Register

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 Associative Memory
Data Register
Mask Register

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 Associative Memory
Data Register
Mask Register
Match Register

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Associative Memory

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Associative Cache

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 Data Lines/Blocks
Multiple consecutive words form a line

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 Data Lines/Blocks
Multiple consecutive words form a line
All data in a line is moved together

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 Data Lines/Blocks
Multiple consecutive words form a line
All data in a line is moved together
Takes advantage of locality of reference

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Associative Cache with a Line
Size of 4 Bytes

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Direct Mapped Cache

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Direct Mapped Cache with a
Line Size of 4 Bytes

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Drawbacks of Direct Mapped
Cache
0000 0000 0000 0000: JUMP 1000H
0001 0000 0000 0000: JUMP 0000H

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Set-Associative Cache

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Set-Associative Cache with a
Line Size of 4 Bytes

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 Data Replacement Policies
FIFO

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 Data Replacement Policies
FIFO
LRU

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 Data Replacement Policies
FIFO
LRU
Random

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 Example

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 Example

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 Example

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 Example

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 Writing Data to Cache
Write back
Write through
Write allocate
Write no-allocate

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 Cache Performance
Hits and misses

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 Cache Performance
Hits and misses
Hit ratio

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 Cache Performance
Hits and misses
Hit ratio
Average memory access time

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Cache Activity - Associative
Cache
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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Cache Activity - Associative
Cache
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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 Cache Activity - Direct
Mapped Cache
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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Cache Activity - Direct Mapped
Cache
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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Cache Activity - 2-Way Set-
Associative Cache
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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Cache Activity - 2-Way Set-
Associative Cache
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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2-Way Set-Associative Cache
with a Line Size of 2
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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2-Way Set-Associative Cache
with a Line Size of 2
A0 B0C2 A0 D1B0 E4 F5A0C2 D1B0G3C2 H7 I6 A0 B0

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 Virtual Memory
Memory Management Unit (MMU)

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 Virtual Memory
Memory Management Unit (MMU)
Swap disk/file

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 Virtual Memory
Memory Management Unit (MMU)
Swap disk/file
Logical address

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 Virtual Memory
Memory Management Unit (MMU)
Swap disk/file
Logical address
Physical address

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Paging - Pages and Frames

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MMU Configuration

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Page Table

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Address Conversion

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Translation Lookaside Buffer

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 Example

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 Example

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Segmentation

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 Fragmentation
Internal fragmentation

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 Fragmentation
Internal fragmentation
External fragmentation

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 Fragmentation
Internal fragmentation
External fragmentation

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 Beyond the Basics
Split cache

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 Beyond the Basics
Split cache
Multilevel page table

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Multilevel Page Table

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Pentium/Windows NT Memory
Management

8 KB

8 KB

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 Pentium/Windows NT Cache
Memory Management
16KB L1 split cache
2-way set-associative
Line size of 32 bytes
TLB used for cache and virtual memory
Pseudo-LRU replacement policy
256K L2 unified cache
4-way set-associative

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 Pentium/Windows NT Virtual
Memory Management
4 GB address space
Low-order 2 GB for individual processes
High-order 2 GB for Windows NT
components
Uses paging, not segmentation
10-bit page directory pointer + 10-bit
offset
Uses the same TLBs as cache memory

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 Summary
Hierarchical Memory Systems
Cache Memory
Virtual Memory
Pentium/Windows Memory System

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