TIMING DIAGRAM

SHREYAS CHAROLA
M.TECH VLSI DESIGN (VIT, VELLORE)
MEFGI,RA JKOT
SHREYAS.CHAROLA@MARWADIEDUCATION.EDU.IN
OUTLINE
TIMING DIAGRAM
T-STATE
INSTRUCTION CYCLE
MACHINE CYCLE
DIFFERENT MACHINE TIMING DIAGRAM
EXAMPLES OF INSTRUCTION CYCLES
What is timing diagram ?
Timing Diagram is the graphical representation of the different
steps required to execute particular instruction with respect to
time i.e. clock signal.
Clock signal
Time taken for the microprocessor and the system to execute an
instruction or program are measured only in terms of the time
period of the clock.
The execution time is represented in T-states. T state is made up
by one clock pulse

Falling
Logic Edge
Rising
level
Edge
T- State
Microprocessor performs an operation in a specific time period i.e. specific clock cycles.
Each clock cycle is called as T-state.
T - STATE

The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.
Machine Cycle
The time required to access the memory or input/output devices is called machine cycle.
The instructions of 8085 require 15 machine cycles containing 36 states (clocks).
The 1st machine cycle of any instruction is always an Op. Code fetch cycle in which the processor
decides the nature of instruction. It is of at least 4-states or it may go up to 6-states.

T1, T2, and T3 clock cycles are used for the basic memory read operation
T4 clock and beyond are used for its interpretation of the opcode
Instruction Cycle
The function of the microprocessor is divided into fetch and execute cycle of any instruction of
a program.
In the normal process of operation, the microprocessor fetches (receives or reads) and executes
one instruction at a time in the sequence until it executes the halt (HLT) instruction.
Thus, an instruction cycle is defined as the time required to fetch and execute an instruction.
Basically 2-steps are followed sequentially with the help of clocks
1. Fetch
2. Execute
Special Case
Note:
Some instructions do not require any machine cycle other than that necessary to fetch the
instruction.
Other instructions, however, require additional machine cycles to write or read data to or from
memory or I/O devices.
To cope up with the slow memories or I/O devices microprocessors have the provisions of
introducing wait cycle within the fetch cycle.
Comparaison between Machine Cycle, T-state,
Instruction cycle

Instruction Cycle

Machine Machine Machine Machine Machine

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

T State 1 T State 2 T State 3 T State 4 T State 5 T State 6

Machine Cycle
There are total seven machine cycles in 8085 Microprocessor.
1. 1.Opcode fetch cycle (4T)
2. 2.Memory read cycle (3 T) 7T states is required
3. 3.Memory write cycle (3 T) 7T states is required
4. 4.I/O read cycle (3 T) 10T states is required
5. 5.I/O write cycle (3 T) 10T states is required
Status Signals
STATUS SIGNALS
MACHINE CYCLE IO/M S1 S0

BUS IDLE 0 0 0
MEMORY WRITE 0 0 1
MEMORY READ 0 1 0
OPCODE FETCH 0 1 1
I/O WRITE 1 0 1
I/O READ 1 1 0
INTERRUPT ACKNOWLEGE 1 1 1
OPCODE FETCH MACHINE CYCLE
INSTRUCTION CYCLE MOV C,A
MEM. ADD INSTRUCTION HEX BYTE OPERATION(MACHIN
CODE CYCLE)
C000H MOV C,A 4FH 1 OPCODE FETCH
 T1 T2 T3 T4
CLK
MACHINE CYCLE (OPCODE FETCH)

A15
A8 C0H HIGH-ORDER MEMROY ADDRESS UNSPECIFIED

LOW-ORDER

AD7
00H 4FH OPCODE
AD0
MEMROY ADDRESS
OPCODE FETCH
MEM. ADD HEX CODE
ALE
C000H 4FH

IO/M
STATUS IO/M = 0, S1 = 1, S0 = 1 OPCODE FETCH
S1 , S0

RD
The Fetch Execute Sequence :
1. The p placed a 16 bit memory address from PC (program counter) to address bus.
Figure : at T1
The high order address, C0H, is placed at A15 A8.
the low order address, 00H, is placed at AD7 - AD0 and ALE is active high.
Synchronously the IO/M is in active low condition to show it is a memory
operation.
2. At T2 the active low control signal, RD, is activated so as to activate read operation; it is to
indicate that the MPU is in fetch mode operation.
At T3:
The active low RD signal enabled the byte instruction, 4FH, to be placed on
AD7 AD0 and transferred to the MPU. While RD high, the data bus will be
in high impedance mode.

At T4: The machine code, 4FH, will then be decoded in instruction decoder.
The content of accumulator (A) will then copied into C register at time state,
T4.
Timing Diagram of Memory Read
Machine Cycle of 8085:
The memory read machine cycle is executed by the processor to read a data byte from
memory. The processor takes 3T states to execute this cycle.
Mov A,M

C000H Opcode of MOV R (3E)

C0 20

H L
20 30 2030 50
00 3E 30 50
Mov M,R
INSTRUCTION CYCLE - MVI A,32H
MEM. ADD INSTRUCTION HEX BYTE OPERATION(MACHIN
CODE CYCLE)
2000H MVI A, 32H 3EH 2 OPCODE FETCH
2001H 32H MEMORY READ

INSTRUCTION CYCLE FOR MVI A,32H

MEM. INSTRUCTION HEX BYTE OPERATION( T-STATES MACHINE
ADD CODE MACHIN CYCLES
CYCLE)
2000H MVI A, 32H 3EH 1st OPCODE 4 M1
FETCH
2001H 32H 2nd MEMORY 3 M2
READ
TOTAL 2 7 2
 T1 T2 T3 T4

MACHINE CYCLE (OPCODE FETCH)

CLK

A15
A8 C0H HIGH-ORDER MEMROY ADDRESS UNSPECIFIED

LOW-ORDER
AD7
AD0 00H 3EH OPCODE
OPCODE FETCH
MEMROY ADDRESS
MEM. ADD DATA
ALE C000H 3EH

IO/M
STATUS IO/M = 0, S1 = 1, S0 = 1 OPCODE
S1 , S0
FETCH
RD
 T1 T2 T3

MACHINE CYCLE (MEMORY READ)

CLK

A15
A8 C0H HIGH-ORDER MEMROY ADDRESS
LOW-ORDER
AD7
AD0 01H 32H DATA
MEMORY READ
MEMROY ADDRESS DATA FROM
MEMORY MEM. ADD DATA
ALE C001H 32H

IO/M
STATUS IO/M = 0, S1 = 1, S0 = 0 MEMORY
S1 , S0
READ
RD

MEMR
Timing Diagram For MVI instruction
(MVI B,05H)
Timing Diagram of Memory Write
Machine Cycle (STA 2065H)
INSTRUTION
STA 2065H
Accumulator 42H

INSTRUCTION CYCLE FOR STA 2065H

MEM. ADD INSTRUCTION HEX CODE BYTE OPERATION(MACHIN CYCLE)

C000H STA 2065H 32H 3 OPCODE FETCH

C001H 65H LOW ORDER ADDRESS
C002H 20H HIGH ORDER ADDRESS

Note: No relationship between no. of bytes of instruction and the no. of operation (Machine
cycle) it has to perform
INSTRUCTION CYCLE STA 2065H
This instruction is 3-byte, however it requires
INSTRUTION
4 machine cycles and 13 T-states. STA 2065H
Acc 42H
INSTRUCTION CYCLE FOR STA C500H
MACHINE Mnemonics Hex Code ADDRESS T-STATES Machine
CYCLE Cycles
1 32H C000H OPCODE 4 M1
STA FETCH

TOTAL 4 1
 T1 T2 T3 T4

MACHINE CYCLE (OPCODE FETCH)

CLK

A15
A8 C0H HIGH-ORDER MEMROY ADDRESS UNSPECIFIED

LOW-ORDER
AD7
AD0 00H 32H OPCODE
OPCODE FETCH
MEMROY ADDRESS
MEM. ADD OPCODE
ALE C000H 32H

IO/M
STATUS IO/M = 0, S1 = 1, S0 = 1 OPCODE FETCH
S1 , S0

RD
STA 2065H
INSTRUCTION CYCLE STA 2065H
This instruction is 3-byte, however it requires
INSTRUTION
4 machine cycles and 13 T-states. STA 2065H
Acc 42H
INSTRUCTION CYCLE FOR STA C500H
MACHINE OPERATIO CONTE ADDRESS T-STATES
CYCLE NS NT
1 OPCODE 32H C000H OPCODE 4 M1
FETCH FETCH
2 MEMORY 65H C001H LOW 3 M2
READ ORDER
ADDRESS

TOTAL 7 2
 T1 T2 T3

MACHINE CYCLE (MEMORY READ)

CLK

A15
A8 C0H HIGH-ORDER MEMROY ADDRESS
LOW-ORDER
AD7
AD0 01H 65H DATA
MEMORY READ
MEMROY ADDRESS DATA FROM
MEMORY
MEM. ADD DATA
ALE C001H 65H

IO/M
STATUS IO/M = 0, S1 = 1, S0 = 0 MEMORY READ
S1 , S0

RD

MEMR
STA 2065H
INSTRUCTION CYCLE STA 2065H
This instruction is 3-byte, however it INSTRUTION
STA 2065H
requires 4 machine cycles and 13 T-states.
Acc 42H

INSTRUCTION CYCLE FOR STA C500H

MACHINE OPERATIO CONTE ADDRESS T-STATES
CYCLE NS NT
1 OPCODE 32H C000H OPCODE 4 M1
FETCH FETCH
2 MEMORY 65H C001H LOW 3 M2
READ ORDER
ADDRESS
3 MEMORY 20H C002H HIGH 3 M3
READ ORDER
ADDRESS

TOTAL 10 3
 T1 T2 T3

MACHINE CYCLE (MEMORY READ)

CLK

A15
A8 C0H HIGH-ORDER MEMROY ADDRESS
LOW-ORDER
AD7
AD0 02H 20H DATA
MEMORY READ
MEMROY ADDRESS DATA FROM
MEMORY MEM. ADD DATA
ALE
C002H 20H

IO/M
STATUS IO/M = 0, S1 = 1, S0 = 0 MEMORY READ
S1 , S0

RD

MEMR
STA 2065H
INSTRUCTION CYCLE STA 2065H
This instruction is 3-byte, however it requires INSTRUTION
STA 2065H
4 machine cycles and 13 T-states.
Acc 42H

INSTRUCTION CYCLE FOR STA C500H

MACHINE OPERATIO CONTE ADDRESS T-STATES
CYCLE NS NT
1 OPCODE 32H C000H OPCODE 4 M1
FETCH FETCH
2 MEMORY 65H C001H LOW 3 M2
READ ORDER
ADDRESS
3 MEMORY 20H C002H HIGH 3 M3
READ ORDER
ADDRESS
4 MEMORY 42H 2065H DATA 3 M4
WRITE
TOTAL 13 4
 T1 T2 T3

MACHINE CYCLE (MEMORY WRITE)

CLK

A15
A8 20H HIGH-ORDER MEMROY ADDRESS
LOW-ORDER
AD7
AD0 65H 42H DATA
MEMORY WRITE
MEMROY ADDRESS DATA FROM MEM. ADD DATA
MPU
ALE 2065H 42H

IO/M
STATUS IO/M = 0, S1 = 0, S0 = 1 MEMORY WRITE
S1 , S0

WR

MEMW
STA 2065H
STA 526Ah ACC = C7h MEM ADD CONTENT/DATA
41FFH STA
4200H 6AH
4201H 52H
526AH C7H
Timing diagram of LDA address
Timing diagram for IN C0H.
OUT 20H
Timing Diagram for Unconditional DAD B
Timing Diagram for Unconditional JM 2100H
(Assume Condition is not satisfied)
Timing Diagram for HLT
Timing Diagram for IN C0h
Timing Diagram for unconditional CALL
Thank You