CPU and Instruction Set

MOKHTAR NIBOUCHE
MOKHTAR.NIBOUCHE@UWE.AC.UK
ROOM 2N36
DEPARTMENT OF ENGINEERING DESIGN AND
MATHEMATICS
FACULTY OF ENVIRONMENT AND TECHNOLOGY
UNIVERSITY OF THE WEST OF ENGLAND
 Learning Outcomes
2

At the end of the lecture you should understand

The role of the Central Processing Unit (CPU)
The formats of different instructions
The role of the status register
Microcontroller Vs Microprocessor
3
PIC16F877 Architecture
 Von Neumann vs. Harvard
5

Microcontrollers featuring a Von-

Neumann architecture (or model) have
only one bus for both data and
instructions (i.e. one memory block and
one 8-bit data bus for an 8-bit micro).
Only a single operation can be
performed by the CPU (simultaneous
operations are not possible).
The CPU can either read an instruction or read/write data
from/to the memory.
As all data is exchanged through these 8 lines, the bus is
overloaded and communication is slow and inefficient.
The Von Neumann architecture is very simple.
 Von Neumann vs. Harvard
6

Microcontrollers featuring a
Harvard architecture have
two different busses. As such,
the CPU can read an
instruction and access data
memory at the same time.
One is 8 bits wide and
connects the CPU to a
memory unit (RAM).
The other bus consists of 12, 14 or 16 lines and connects the
CPU to a different memory unit (ROM).
The Harvard architecture is in general more complex
 Introduction
7

The Central Processing Unit (CPU) is regarded as the brain

of the microcontroller.
The CPU uses the information in the programme memory
(instructions) to control the operation of the
microcontroller, where many of these control operations
(instructions) operate on data memory.
To carry out these operations on data, the CPU requires an
Arithmetic and Logic Unit (ALU).
The ALU performs arithmetic and logic operations. It also
controls status bits, which are part of the status register.
The set of operations (instructions) that the CPU recognises
is called instructions set (35 instructions for the PIC
P16F877) Reduced Instruction Set Computer (RISC).
 Arithmetic and Logic Unit
8
The general purpose ALU is
8-bits wide.
It performs arithmetic and
Boolean operations between
the data in the accumulator
W (or working register) and
any register file f.
The operations include
addition, subtraction, shift
and logical operations.
In two operand instructions, one operand is the accumulator
W and the other operand is a file register f (e.g. ADDWF f, d),
or an immediate constant (e.g. MOVLW k).
 Arithmetic and Logic Unit
9
In single operand
instructions, the operand is
either the accumulator W
(e.g. CLRW) or a file register
f (e.g. BCF f, b).
Depending on the
instruction, the ALU may
affect the certain values in
the status register (carry (C),
Digit Carry and Zero (Z)).
Note that the 8-bits accumulator W, which extensively used in
ALU operations is not an addressable register.
 Instruction Set
10

All the instructions that are recognised by a particular

microcontroller (e.g. MOVLW k or CLRW).
The number of these special words depends on the type of
microcontroller.
A reduced instruction set computer or RISC
microcontroller has a small number of instructions. The
microcontroller recognises and executes basic instructions
only (addition, subtraction, etc ..). More complex
operations use a combination of the available instructions.
A complex instruction set computer or CISC
microcontroller has a higher number of instructions
(200+). Offers higher speed and more complex
instructions.
 Format
11

Byte Oriented file register operations

13 8 7 6 0
OPCODE d f(File)

d is the destination
d = 0 for destination W (Accumulator or Working Register)
d = 1 for destination f

f is a 7-bit file register address

Examples: MOVWF f ; Move W to f
ADDWF f, d ; Add W and f
ANDWF f,d ; AND W and f
 Format
12

Bit Oriented file register operations

13 10 9 7 6 0
OPCODE b f(File)

b is a 3-bit address
f is a 7-bit file register address
Examples: BCF f, b ; Bit clear f
BSF f, b ; Bit set f
 Format
13

Literal and Control Operations

General
13 8 7 0
OPCODE K (literal)

k is an 8-bit immediate value

Examples : MOVLW k ; Move k to W
ADDLW k ; Add k to the W
 Format
14

Literal and Control Operations

CALL and GOTO
13 11 10 0
OPCODE K (literal)

k is an 11-bit immediate value

Examples: GOTO k ; Go to address

CALL k ; Call subroutine

 Status Register
15

The status register

contains the arithmetic
status of the ALU, the
RESET status and the
bank select bits for data
memory.
As it controls the data
memory banks (4
banks for the P16F877),
a status register is
dedicated to each bank.
It is located in the same
relative position for
each bank.
 Status Register
16

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7 IRP: register Bank Select bit (used for indirect addressing).
bit 6-5 RP1-RP0 :Register Bank Select bits (used for direct addressing).
bit 4 TO : Time-out bit
bit 3 PD : Power down bit
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF)
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF)
 Status Register
17

It is recommended that only the following instructions

BCF (bit clear f)
BSF (bit set f)
SWAPF (swap nibbles in f)
MOVWF f (move W to f)
Are used to alter the status register as they dont affect the
Z, DC and C bits.
 Memory Organisation
18

The memory of the P16F877 device consists of two separate

memory blocks: a programme memory and a data
memory.

Each memory block has its own bus (Harvard architecture).

Access to each block can happen during the same oscillator
cycle.
The data memory block can be broken down into general
purpose RAM and Special Function Registers (SFR).
 Programme Memory Organisation
19

The P16F877 device has a 13-bit

programme counter capable of
addressing an 8k-14 programme
memory space.
The width of the programme
memory bus is 14 bits wide.
All instructions are single word
(8k instruction space)
The programme memory space is
divided into 4 pages of 2k words
each (why is that?).
The programme space has also an
8 level deep stack.
The Programme Counter (PC)
specifies the address of the
instruction to be fetched from for
execution.
 Programme Memory Organisation
20

To select any memory page, the

high bits of the programme
counter (PC) have to be
modified.
This is done by writing the
desired value into an SFR
called PCLATH (Programme
Counter Latch High).
In case sequential instructions
are executed, the programme
counter will cross the page
boundaries without any
external intervention.
 Data Memory Organisation
21

The data memory consists of a

special function registers (SFR)
space and a general purpose
registers (GPR) space.
SFRs control the operation of
the device (core and
peripherals).
GPRs are used for data
storage.
The data memory space is split
into 4 different banks.
To select a bank, control bits
from the status register
(STATUS <7:5>) have to be
modified.
 Data Memory Organisation
22

Moving data from one register

to another is not permitted.
To move data from one
register to another, the W
register has to be used (2
cycles).
The entire data memory can be
accessed either directly or
indirectly.
Bits RP0/RP1 (STATUS <6:5>)
are used in direct addressing.
Bit IRP (STATUS <7>) is used
in indirect addressing (in
combination with the File
Select Register (FSR)).
 Example
23

; SETUP ; MAIN
include"P16F877.INC" start movlw 0

movwf PORTD
TIMREG EQU H'0020' loop incf PORTD,F
delval EQU H'0005' call delay
nop
; PORT SETUP goto loop
Banksel TRISD
clrf PORTD ; DELAY SUBROUTINE
banksel PORTD delay movlw delval
movwf TIMREG
time decfsz TIMREG,F
goto time
return
end
 Further Reading
24

PIC 16F87X Data Sheet 28/40-pin 8-bits CMOS flash

Microcontrollers(DS30292C)