Lesson 2:

Topic:

A. General FPGA Programming Techniques

Agenda
FPGA Palette
Basic FPGA VI
Parallelism and Shared Resources
Integer Math Issues
FPGA Palette
FPGA specific functions
Programming structures
Device I/O
Arithmetic and Boolean Logic
Arrays and clusters
Timing
Math and control functions
Synchronization and FIFOs
Lookup tables
Basic FPGA VI
F=(A+B)CD
LabVIEW Mapped to FPGA
Implementing Logic on FPGA: F =(A+B)CD

A
B
C
D
Compile Process and Server

Convert LV diagram to intermediate files

Send intermediate files to the compile server
Compiles VIs for FPGA
Returns FPGA bitstream to LabVIEW
Bitstream is stored in VI
Compile
Server
LabVIEW environment is a client
Can disconnect from server and reconnect while compiling
Download
Occurs automatically
after a compile
Windows OS initiated by the run
LabVIEW FPGA Module button
FPGA VI
Target FPGA
Bit File Embedded Download FPGA VI (actually
the bit file)
Interactive Mode
Interact with VI on FPGA
through Front Panel
Windows OS No Debugging
LabVIEW FPGA Module VI is running in the FPGA

FPGA VI Target FPGA

(Front Panel)
FPGA VI
Updates (running)
Host PC Interactive Mode Interact with FPGA through
host PC based Front Panel
Allows you to do other
Windows OS processing in Host VI

VI Target FPGA
(Front Panel)
FPGA VI
Updates (running)
Windows Target Mode

Windows OS Run FPGA VI on Windows

LabVIEW FPGA Module Software Emulation
(targeted to Windows) No hardware timing
Debugging possible
Check logic before compile
FPGA VI
Exercise 2.1
Create a VI which adds two
numbers and runs a
benchmark in parallel that
determines how fast code is
running
exercise_2.1.doc

Open the Spartan 3E

example and build the
program
Exercise_2.1Getting Started Spartan 3E.doc
Shared Resources
Before a task can begin using a shared resource, it must wait until it
is free.

Task 1 Shared Task 2

Resource
Running Waiting

After Task 1 finishes, Task 2 can proceed.

Task 1 Shared Task 2

Resource
Waiting Running
Sharing Resources

Shared Resources:
Digital Outputs
Memory/FIFOs
Non-Reentrant VIs
Local Variables
Shared Resources Example
Sharing VIs (non-Reentrant VIs)
Non-Reentrant (Default)
The VI is shared
Only one instance on the FPGA device
Reentrant VI
Separate set of gates on the FPGA device for each instance
on the diagram (uses more space)

Configure by Right-Clinking on Resource and selecting Properties

Integer Math

No floating point
Singles and doubles type
are not supported
Integer Math

Scaling of data required for analysis and output operations

Replaces floating point multiplication/division on the FPGA
Most useful for 16-bit integers, use 32-bit width during calculation
Operations
Multiply value by integer scaling factor
Scale result by a predetermined power of 2
Combined effect provides non-integer multiplication
Integer Math
For variable scaling, you can determine and set the scaling
factor and bit shift from the host application

For example: Scaling Factor: 11500

Downshift: -14 bits
Result Multiplication: 11500 / 16384 = 0.7019
Integer Math
Saturation Arithmetic VIs
used to handle or avoid
integer overflow when
performing mathematical
operations
Two types of results when
overflow
-Saturate
-Wrap
Other Examples to Learn More

\FPGA Fundamentals- in the examples folder