Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 14: Combinational Circuit Design

 Differential PT Logic

Accept true and complement inputs and produce true and

complement outputs

No need of intermediate inverters

 Differential PT Logic
Differential Pass Transistor Logic
B B B B B B

A A A

F=AB B F=A+B A F=AB

B

A A A
F=AB F=A+B F=AB
B B A
AND/NAND OR/NOR XOR/XNOR
 Design Rules: PT Logic

B Output of the pass transistor should not
1.5/0.25
drive the gate of another pass transistor
0.5/0.25

A Separate charging and discharging path to

0.5/0.25

beBprovided to the output

F = AB
0
0.5/0.25

Simultaneous path from Vdd to ground has

to be avoided
 Advantages: PT Logic

B Ratio-less
1.5/0.25

0.5/0.25

A Less number of transistors

0.5/0.25
B
F = AB
0
0.5/0.25

Less power dissipation

 Disadvantages: PT Logic

B Reduced noise margin
1.5/0.25

0.5/0.25
Multiple Vt drop
A
0.5/0.25
B
F = AB
0
Sneak path
0.5/0.25

Dual rail logic

 Solution
There are three solution to address this problem

Level restoration
Zero threshold transistors
Transmission gate logic
Solution 1: Level Restorer

Level Restorer

Mr
B = VDD off
M2
Mn
x= 0
A=0 Out =1
M1
 Solution 1: Level Restorer

Level Restorer

Mr
B = VDD ON
VDD
M2
A = VDD Mn
x = VDD-Vtn
Out =0
M1

No static power dissipation

Increased complexity
 Solution 1: Level Restorer

Level Restorer

Mr
B = VDD ON
M2
A Mn
x = VDD

M1

Problem when Transition of Node X from high to low

Pull down network (Mn) should be stronger

 Solution 2: Zero Vt

low VT transistors
In2 = 0V A = 2.5V
on

Out

off but leaking

In1 = 2.5V B = 0V
sneak path

Static power dissipation

 Solution 3: Transmission Gate
Transmission gate Logic
S
S

In Out
In Out

S
S

Construct 2:1 Mux Y = AB+AC+ABC

Construct AND and OR Gate

Thank You