FILKOM | UB

KOM 15201

Desain Sistem Digital

FILKOM | UB

MATAKULIAH : Desain Sistem Digital

KODE/ STATUS : KOM 15201
sks :3
Dosen : Dahnial Syauqy, ST, MT
Clock divider (dengan prescaler)
Rumus prescaler:
(Clock_source/clock_intended)/2
Contoh:
Spartan 3-e board internal oscillator, 50 Mhz yang dibagi menjadi 1 Hz.
Maka buat variabel prescaler dengan nilai
Prescaler= (50000000/1)/2=25000000

Signal clock_tujuan_1Hz: STD_LOGIC;

process (clock_sumber_50Mhz)
variable counter: integer range 0 to 25000000;
begin
if clock_sumber_50Mhz'event and clock_sumber_50Mhz = '1' then
if counter < 25000000 then
counter := counter + 1;
else
counter := 0;
clock_tujuan_1Hz <= not clock_tujuan_1Hz;
end if;

Slide 3
end if;
end process;
Agenda

Introduction
Review Sistem Digital
FPGA design dengan Xilinx
Rangkaian kombinasional
Rangkaian Enkoder, Decoder, Multiplekser dll
Konsep-konsep tambahan dalam pemrograman
Flip flop
-----------------------------------UTS-------------------------------------
Rangkaian Counter & Finite State Machine (FSM)
Materi pengayaan
Desain project dan presentasi
-----------------------------------UAS-------------------------------------

Slide 4
2 December 2017
Sequential Logic Design in VHDL
The design of sequential circuits in VHDL requires the use of the process
statement.

Sequential Circuit:
Regular sequential circuit.
The state transitions in the circuit exhibit a regular pattern, as in a counter
or shift register. The next-state logic is constructed primarily by a
predesigned, regular component, such as an incrementor or shifter.
FSM.
The state transitions in the circuit do not exhibit a simple, repetitive pattern.
The next-state logic is constructed by random logic and synthesized from
scratch. It should be called a random sequential circuit, but is commonly
known as an FSM (finite state machine).

Slide 5
2 December 2017
Coding style

Slide 6
2 December 2017
Basic block of VHDL sequential programming

Entity

Clocking (and reset) process block

Architecture

Next state logic block

Output logic block

Slide 7
Ketiga blok adalah concurrent, sehingga tidak harus urut
Ketiganya berjalan secara parallel karena concurrent
2 December 2017
4 bit counter up/down
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity counter_updown is 0000 reset

Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
up : in STD_LOGIC;
down : in STD_LOGIC; 0001
q : out STD_LOGIC_VECTOR (3 downto 0)); down
end counter_updown;

architecture Behavioral of counter_updown is

signal r_reg: unsigned (3 downto 0); 0010
signal r_next: unsigned (3 downto 0);
begin
--clocked process
process(clock, reset) 0011
begin
if (reset='1') then
r_reg<=(others=>'0');
elsif (clock'event and clock='1') then
r_reg<=r_next;
end if;
end process; up
--next state logic
r_next <= r_reg + 1 when up='1' and down='0' else
r_reg - 1 when down='1' and up='0' else
r_reg;

--output logic 1111

Slide 8
q<=STD_LOGIC_VECTOR (r_reg);

end Behavioral;
8 bit counter up/down

8 bit counter up/down dengan opsi

load (dari d), enable, dan
synchronous clear

Slide 9
2 December 2017
Shift register left/right

Slide 10
2 December 2017
FSM
An FSM (finite state machine) is used to model a system that transits
among a finite number of internal states.
The transitions depend on the current state and external input.
Unlike a regular sequential circuit, the state transitions of an FSM do not
exhibit a simple, repetitive pattern.
This is different from the next-state logic of a regular sequential circuit,
which is composed mostly of structured components, such as
incrementors and shifters.

Slide 11
2 December 2017
 The basic block diagram of an FSM is the same as that of a regular sequential circuit.
It consists of a state register, next-state logic, and output logic.
An FSM is known as a Moore machine if the output is only a function of state, and is
known as a Mealy machine if the output is a function of state and external input.

Slide 12
2 December 2017
FSM example

Slide 13
declaration
State declaration in architecture

Contoh:

Slide 14
2 December 2017
Contoh-contoh FSM
Answering machine

Slide 15
2 December 2017
Contoh-contoh FSM
Soda machine

Slide 16
2 December 2017
 Contoh-contoh FSM Lift manual 2 lantai

Up=1 & down=0 & sensor lt 1=1 /

Motor up=1
Up=0 & down=0 / Motor down=0
Motor up=0
Motor down=0

State 1 State 2
lt0 lt1

Up=0 & down=0 /

Motor up=0
Up=0 & down=1 & sensor lt 0=1 / Motor down=0
Motor up=0
Motor down=1

Slide 17
2 December 2017
library IEEE;
--next state logic
use IEEE.STD_LOGIC_1164.ALL;
Next_state_proc: process(state_reg,up,down,sensor_lt1,sensor_lt0)
begin
entity fsmlift is
case state_reg is
Port ( clock : in STD_LOGIC;
when lt0 =>
up : in STD_LOGIC;
if up='1' and down='0' then if sensor_lt1='1' then
reset : in STD_LOGIC;
state_next<=lt1;
down : in STD_LOGIC;
end if;
sensor_lt0 : in STD_LOGIC;
end if;
sensor_lt1 : in STD_LOGIC;
when lt1 =>
motor_up : out STD_LOGIC;
if up='0' and down='1' then if sensor_lt0='1' then
motor_down : out STD_LOGIC);
state_next<=lt0;
end fsmlift;
end if;
end if;
architecture Behavioral of fsmlift is
end case;
type state_type is (lt0,lt1);
end process;
signal state_reg: state_type;
- combinational logic and output (MEALY)
signal state_next: state_type;
output_proc: process(state_reg,up,down)
begin
begin
--clocked process
case state_reg is
state_proc: process(clock,reset)
when lt0 =>
begin
if up='1' and down='0' then
if reset='1' then
motor_up<='1';
state_reg<=lt0;
motor_down<='0';
elsif clock'event and clock='1' then
else
state_reg<=state_next;
motor_up<='0';
end if;
motor_down<='0';
end process;
end if;
when lt1 =>
if up='0' and down='1' then
motor_up<='0';
motor_down<='1';

Slide 18
else
motor_up<='0';
motor_down<='0';
end if;
end case;
end process;
end Behavioral;
TUGAS (kel. besar)
Buatlah FSM menggunakan pemrograman VHDL untuk sistem berikut:
- Memiliki 2 input berupa push button (PB1 dan PB2) dg alamat site: V4 dan K17
- Memiliki 4 output berupa LED dg alamat site:

- State default LED semua mati (0000)

- Saat PB1 ditekan 1x, maka akan pindah ke state berikutnya yakni LED menyala
0001, jika PB1 ditekan 1x lagi maka akan pindah lagi ke state selanjutnya yakni
LED menyala 0010, dst seperti tergambar dalam diagram state berikut:
PB1 PB1
PB1 1 2 15 PB1
PB2 PB2
default PB2

- Jika PB2 ditekan, maka state akan direset ke state default, yakni semua LED mati
(0000)
- Buat program VHDLnya, konfigurasi planahead sekaligus file *.bit-nya untuk

Slide 19
selanjutnya di download ke board xilinx minggu depan di kelas!

2 December 2017
 W-4

Slide 20
2 December 2017