Presentation

Fabrication Process Of
Integrated Circuits
 Group Members

Zeeshan Jabbar (Sp15-Bee-110)

M.Hamza Fayyaz(Sp15-Bee-111)

Anjum Aftab Mirza(Sp15-Bee-112)

 What is VLSI?
Process of creating IC(Integrated Circuits)
Combination of Thousands Transistors on a single Chip

When?
VLSI Technology Began in 1970s
When Semiconductors and telecommunication technologies been developed
Microprocessor is also a part of VLSI Technology.
 SOFTWARE USED IN VLSI DESIGN
VERILOG SOFTWARE
Verilog is hardware descriptive language which are basically used to
describe a Digital system.
Verilog basically define a Top-Down Design or Bottom-Up Design
Approach.
Top-Down VLSI Design Techniques
 Here We Explain Fabrication Process
P-Substrate Formation N-well Formation
+ Photo Lithography
+Photo-Resist
Oxidation

Formation of N-
Diffusion Stripping off protective
Etching
layer

Poly silicon Layer Alignment Poly silicon Patterning

P-Diffusion Same As
Metallization Contacts Formation N-Diffusion
 Types Of Fabrication:

N-Well P-Well Twin-Tub

Fabrication Fabrication Fabrication
 We Discuss N-Well Fabrication:
N-Well Fabrication:

Here we take P-substrate blank wafer.

Where we take n+ as the Drain and Source
Channel is created between n-well.
Fourth terminal as P+ diffusion region
 Step No : 01

P-Substrate Formation

There is a blank wafer on which we make substrate

Firstly, we take P-substrate because we have to form N-Well fabrication.

P-Substrate

P-Substrate Blank Wafer

 Oxidation
We put P-Substrate in the furnace where temperature is 1000C
Oxidation Process is done by high oxygen and hydrogen purity.

This Oxidation layer is basically used for insulation and also for the Gates.

Dry Oxide

Si + O2 SiO2

Wet oxide

Si + 2 H2O SiO2 + 2 H2 Furnace for Oxides

Oxidation On P-Substrate

We clearly see the Silicon

Dioxide Layer on P-
Substrate
SiO2

P-Substrate
 Step N0 : 02

Photo Resistor

A light sensitive Polymer

Thats soften upon exposed to light.
After getting elusion spin at 300 rpm
To get uniform layers of photo-sensitive material Approximately 0.5-1m

Photo Resistor
SiO2

P-substrate
 Masking

Process Of transferring a desire pattern on wafer

Mainly known as Optical mask.
Expose to light through optical mask
Types of masking:
Direct Contact
Proximity
Projection
 Step
PHOTO LITHOGRAPHY

3
N-Mask is opaque and transparent
regions.
N-Mask
These Plates are placed on different on
Wafer and place very precisely
Negative photo resist ,this area is hardened and
U-V Rays N-Mask exposed to UV rays.
Positive Photo resist layer become soften
and removed by acidic or basic solution
---------------------
Photo Resistor Photo Resistor
SiO2 SiO2

P-substrate P-substrate
 ETCHING Step No:
04
Wafer is immersed in acidic and basic solution and clean the exposed layer of photo
resistor
Depends on the material used to be etched out
Example like in Silicon or Poly silicon we use Hydro fluoric Acid
Nitride we use phosphoric Acid

Photo Resistor Photo Resistor

SiO2 SiO2

After
HCl
Bath
P-substrate P-substrate
Removal Of Protective Layer
Step No : 05
Removes through Chemical Reaction
Like we use fuming Nitric acid or exposure to Oxides

Finally Removes the photo resistive layer or protective Layer

Photo Resistor

SiO2 SiO2

Nitric
Acid
Or
Oxides
P-substrate P-substrate
 N-Well Diffusion Step No : 06

Make selective Diffusion Only by two steps

Pre-Deposition
Drive-In
Pre-Deposition:
Wafer is heated in 1000C
Doping atoms like (Phosphorus and Boron with Inert Gas)
Diffusion is placed on the silicon forming a saturation of Dopant atom.
Temperature goes to 1300C
Concentration depends on Duration of Doping
Drive-In
Wafer is heated in inert Gases SiO2
Distributes Atoms more uniformly
and to higher depth
N-Well
P-substrate
 Removal Of Silicon Dioxide Layer

Now again take a chemical reaction of

wafer with HF(Hydro fluoric acid)
Only to Remove the silicon dioxide layer

SiO2
N-Well

N-Well P-substrate
P-substrate
 Poly Silicon Layers

C h e m i c a l Va p o r D e p o s i ti o n
Thin Gate Oxide:
Poly silicon layer is generally formed by silane at Conducting layer that
about 1000C connect the underlying
Then silicon is reacted with the oxygen at source or drain.
Dielectric layer that
700C to give Aluminum and nitride and also
silicon dioxide deposited on the Wafer. separate gate terminal
This Layer is generally thick oxides layer from source or drain.
Layer is normally
Aluminum is then vaporized to
compose of Aluminum or
deposited on the wafer
dry oxides.

Poly silicon

N-Well THIN OXIDE

P-substrate LAYER
 Poly silicon Patterning

We first put a photo resist on the

Poly silicon Poly silicon layer
Then we put a masking on which
N- Photo part we want to aligned
P-substrate Well Resist Thin gate Oxide are made for
transistors.
Poly silicon is used because it
doesnt melt in the further process.

Poly silicon Thin Oxide Gate

Masking
Poly silicon Poly silicon

N- N-
Well Well
P-substrate After Etching P-substrate
 Self Alignment

Poly silicon gives precise alignment for the source and Drain
Now, protective layer of Oxide is form
Use Masking process to make small gaps for n+ doping

Protective Layer Of Oxides

Poly silicon Poly silicon

N- N-
Well Align for Well
P-substrate P-substrate
Doping
 Ion Implantation
Low temperature Process

Doping ion are accelerated to target solid material

Changes electrical ,Physical and chemical properties

Examples
Advantages:

Precise Control of Dose and Depth

Wide selection of Masking
Material like(photo resist , oxide,
poly silicon)
Less sensitive to surface cleaning
process
Use in semi-conductor fabrication
 n+ Doping in the wafer
n+ usually done through ion implantation
Some time called n-Diffusion

-------------------------------
n+ Diffusion

N-well

P-Substrate
n+ Diffused On Wafer
n+ Diffusion

n+ n+ n+

N-well
P-Substrate

AFTER ETCHING PROCESS OXIDES LAYER IS REMOVED

n+ n+ n+

N-well
P-Substrate
 P-Diffusion

-------------------------------
P-Diffusion

n+ n+ n+

N-well
P-Substrate

ION IMPLANTATION

p
p+ n+ n+ p+ n+
+

N-well
P-Substrate
 Contacts
Firstly ,thick layer of Oxide is pressed on the wafer
This is a protective layer which protect other parts from environment .
Cut the part where we connects terminal.
Cut through the etching and same as above process

------------------------------
Contacts Thick Oxide Layer

p
p+ n+ n+ p+ n+
+

N-well
P-Substrate
 METALLIZATION Through patterning and masking we get rid
of excess metal

------------------------------------
Metals
Splutter metal on the surface of wafer

p
p+ n+ n+ p+ n+
+

N-well
P-Substrate
 END RESULT OF FABRICATION

N-MOS P-MOS

p
p+ n+ n+ p+ n+
+

N-well
P-Substrate
 REFFERENCE:

Lecture slides .

Ion-implantation MSE-630 (California State University )

Cheming Hu Ch3
Thank you