LAYOUT DESIGN RULES

Mask Generation
• Mask Design using Layout Editor
– user specifies layout objects on different layers
– output: layout file
• Pattern Generator
– Reads layout file
– Generates enlarged master image of each mask layer
– Image printed on glass
• Step & repeat camera
– Reduces & copies image onto mask
– One copy for each die on wafer
– Note importance of mask alignment

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 Symbolic Mask Layers
• Key idea:
– Reduce layers to those that describe design
– Generate physical layers as needed
• Magic Layout Editor: "Abstract Layers”
– metal1 (blue) - 1st layer metal (equiv. to physical layer)
– Poly (red) - polysilicon (equivalent to physical layer)
– ndiff (green) - n diffusion (combination of active, nselect)
– ntranistor (green/red crosshatch) - combined poly, ndiff
– pdiff (brown) - p diffusion (combination of active, pselect)
– ptransistor (brown/red crosshatch) - combined poly, pdiff
– contacts: combine layers, cut mask

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 About Magic
• Scalable Grid for Scalable Design Rules
– Grid distance: l (lambda)
– Value is process-dependent:
l = 0.5 X minimum transistor length
• Painting metaphor
– Paint squares on grid for each mask layer
– Layers to interact to form components (e.g.
transistors)

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 Mask Layers in Magic
• Poly (red)
• N Diffusion (green)
• P Diffusion (brown)
• Metal (blue)
• Metal 2 (purple)
• Well (cross-hatching)
• Contacts (X)

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 Magic User-Interface
• Graphic Display Window Cursor

– Cursor
– Box - specifies area to paint
• Command window
(not shown)
– accepts text commands Box
:paint poly
: paint red
:paint ndiff
:paint green
Paint Paint Paint
:write (poly) (ntransistor) (pdiff)
– prints error & status messages

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 Layer Interaction in Magic
• Transistors - where poly, diffusion cross
– poly crosses ndiffusion - ntransistor
– poly crosses pdiffusion - ptransistor
• Vias - where layers connect
– Metal 1 connecting to Poly - polycontact
– Metal 1 connecting to P-Diffusion (normal) - pdc
– Metal 1 connecting to P-Diffusion (substrate contact) - psc
– Metal 1 connecting to N-Diffusion (normal) - ndc
– Metal 1 connecting to N-Diffusion (substrate contact) - nsc
– Metal 1 connecting to Metal 2 - via

January 8, 2018 17
 Magic Layers - Example
nsc p-transistor

metal1

nwell pdc
polycontact
metal1
poly

polycontact
poly
metal1

psc ndc ndc

ntransistor

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 Why we need design rules
• Masks are tooling for manufacturing.
• Manufacturing processes have inherent
limitations in accuracy.
• Design rules specify geometry of masks which
will provide reasonable yields.
• Design rules are determined by experience.

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 Manufacturing problems
• Photoresist shrinkage, tearing.
• Variations in material deposition.
• Variations in temperature.
• Variations in oxide thickness.
• Impurities.
• Variations between lots.
• Variations across a wafer.

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 Transistor problems
• Varaiations in threshold voltage:
– oxide thickness;
– ion implanatation;
– poly variations.
• Changes in source/drain diffusion overlap.
• Variations in substrate.

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 Wiring problems
• Diffusion: changes in doping -> variations in
resistance, capacitance.
• Poly, metal: variations in height, width ->
variations in resistance, capacitance.
• Shorts and opens:

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 Oxide problems
• Variations in height.
• Lack of planarity -> step coverage.

metal 2
metal 2 metal 1

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 Via problems
• Via may not be cut all the way through.
• Undesize via has too much resistance.
• Via may be too large and create short.

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 MOSIS SCMOS design rules
• Designed to scale across a wide range of
technologies.
• Designed to support multiple vendors.
• Designed for educational use.
• Ergo, fairly conservative.

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 l and design rules
• l is the size of a minimum feature.
• Specifying l particularizes the scalable rules.
• Parasitics are generally not specified in
l units

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 Design Rules
• Typical rules:
– Minumum size
– Minimum spacing
– Alignment / overlap
– Composition
– Negative features

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 Types of Design Rules
• Scalable Design Rules (e.g. SCMOS)
– Based on scalable “coarse grid” - l (lambda)
– Idea: reduce l value for each new process, but keep rules the same
• Key advantage: portable layout
• Key disadvantage: not everything scales the same
– Not used in “real life”
• Absolute Design Rules
– Based on absolute distances (e.g. 0.75µm)
– Tuned to a specific process (details usually proprietary)
– Complex, especially for deep submicron
– Layouts not portable

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 SCMOS Design Rules
• Intended to be Scalable
– Original rules: SCMOS
– Submicron: SCMOS-SUBM
– Deep Submicron: SCMOS-DEEP
• Pictorial Summary: Book Fig. 2-24, p. 27
• Authoritative Reference: www.mosis.org

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 SCMOS Design Rule Summary
• Line size and spacing:
– metal1: Minimum width=3l, Minimum Spacing=3l
– metal2: Minimum width=3l, Minimum Spacing=4l
– poly: Minimum width= 2l, Minimum Spacing=2l
– ndiff/pdiff: Minimum width= 3l, Minimum Spacing=3l,
minimum ndiff/pdiff seperation=10l
– wells: minimum width=10l,
min distance form well edge to source/drain=5l
• Transistors:
– Min width=3l
– Min length=2l
– Min poly overhang=2l

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 SCMOS Design Rule Summary
• Contacts (Vias)
– Cut size: exactly 2l X 2l
– Cut separation: minimum 2l
– Overlap: min 1l in all directions
– Magic approach: Symbolic contact layer min. size 4l X 4l
– Contacts cannot stack (i.e., metal2/metal1/poly)
• Other rules
– cut to poly must be 3l from other poly
– cut to diff must be 3l from other diff
– metal2/metal1 contact cannot be directly over poly
– negative features must be at least 2l in size
– CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal

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 Design Rule Checking in Magic
• Design violations
displayed as error paint
• Find which rule is violated
with ":drc why”
Poly must overhang
transistor by at
least 2 (MOSIS rule
#3.3)

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 Scaling Design Rules
• Effects of scaling down are positive
• See book, p. 78-79 - if “everything” scales,
scaling circuit by 1/x increases performance by
x
• Problem: not everything scales proportionally

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 Aside - About MOSIS
• MOSIS - MOS Implementation Service
• Rapid-prototyping for small chips
– Multi-project chip idea - several designs on the same wafer
– Reduced mask costs per design
– Accepts layout designs via email
– Brokers fabrication by foundries
(e.g. AMI, Agilent, IBM, TSMC)
– Packages chips & ships back to designers
• Our designs will use AMI 1.5µm process
(more about this later)

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 Aside - About MOSIS
• Some Typical MOSIS Prices (from www.mosis.org)
– AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) $1,080
– AMI 1.5µm 9.4mm X 9.7mm $17,980
– AMI 0.5µm 0-5mm2 $5,900
– TSMC 0.25µm 0-10mm2 $15,550
– TSMC 0.18µm 0-7mm2 $24,500
– TSMC 100-159mm2 $63,250 + $900 X size
• MOSIS Educational Program (what we use)
– AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) FREE*
– AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE*
*sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., |
AMI, Inc., DuPont Photomasks, and MOSIS

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 Layout Considerations
• Break layout into interconnected cells
• Use hierarchy to control complexity
• Connect cells by
– Abutment
– Added wires
• Key goals:
– Minimize size of overall layout
– Meet performance constraints
– Meet design time deadlines
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 Hierarchy in Layout
• Chips are constructed as a hierarchy of cells
– Leaf cells - bottom of hierarchy
– Root cells - contains overall cell
• Example - hypothetical “UART”
– Pad frame - “ring” that contains I/O pads
– Core - contains logic organized as subcells
• Shift register
• FSM
• Other cells

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 Wires

6 metal 3

3 metal 2

3 metal 1

3 pdiff/ndiff

2 poly

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 Transistors

2
2
3
3

1
5

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 Vias
• Types of via: metal1/diff, metal1/poly,
metal1/metal2.

4 4
1

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 Metal 3 via
• Type: metal3/metal2.
• Rules:
– cut: 3 x 3
– overlap by metal2: 1
– minimum spacing: 3
– minimum spacing to via1: 2

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 Tub tie

4
1

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 Spacings
• Diffusion/diffusion: 3
• Poly/poly: 2
• Poly/diffusion: 1
• Via/via: 2
• Metal1/metal1: 3
• Metal2/metal2: 4
• Metal3/metal3: 4

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 Overglass
• Cut in passivation layer.
• Minimum bonding pad: 100 m.
• Pad overlap of glass opening: 6
• Minimum pad spacing to unrelated metal2/3:
30
• Minimum pad spacing to unrelated metal1,
poly, active: 15

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 Stick diagrams (1/3)
• A stick diagram is a cartoon of a layout.
• Does show all components/vias (except
possibly tub ties), relative placement.
• Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.

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 Stick Diagrams (2/3)
• Key idea: "Stick figure cartoon" of a layout
• Useful for planning layout
– relative placement of transistors
– assignment of signals to layers
– connections between cells
– cell hierarchy

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 Stick Diagrams (3/3)

January 8, 2018 47
 Example - Stick Diagrams (1/2)

Alternatives - Pull-up Network

Circuit Diagram. Pull-Down Network Complete Stick Diagram

(The easy part!)

January 8, 2018 48
 Example - Stick Diagrams (2/2)

January 8, 2018 49
 Layout Design Rule summary
•Width of Poly – 2l
•Active contact - 2l*2l
• Overlap Spacing contact and metal – 1 l
• Spacing between contacts – 3 l
• Overlap Spacing contact and Active – 2 l
Overlap Spacing Active with diffusion – 3 l
• Overlap Spacing Diffusion with n- Well – 2 l
 Step - 1
• Draw the contact - 2l*2l
 Step - 2
• Cover the contact with Metal1 –
– Spacing - 1 l
 Step - 3
• Draw the diffusion – 2λ spacing

2λ

4λ
 Step - 4
• Draw the Poly – Width - 2λ
Forms N-mos Transistor

2λ
 Step - 5
• Repeat the steps to form P-mos transistor.
Draw n-Well with the dimension 3λ
3λ
 Step - 6
Repeat the Steps
to Form N-mos
transistor.
Connect the
poly.
 Step - 7
• Draw the Metal rail – width – 3λ to represent
Vdd and Gnd.

Vdd 3λ

Gnd
 Step - 8
• Connect the contacts and name the terminal.