ECE-E434 Digital Electronics

Lectures 16 & 17: Decoder Circuits;

ROM

Instructor: Pouya Dianat

Nov 16 & 21 2017
 Announcements
• Term project is uploaded on Bblearn.
• HW set 5 is due on Friday Dec 1 2017.
• Special Assignment:
– Should be completed within 6 hours from the first
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 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Row Address Decoder

• For 2M word lines, a decoder circuit translates the M-bit address into a high voltage
on the target line.
• Assume M=3, therefore address bits A0, A1, A2 and Word Lines W0, W1, …, W7:

A0 A1 A2 W
0 0 0 W0 = A0 + A1 + A2
0 0 1 W1 = A0 + A1 + A2
0 1 0 W2 = A0 + A1 + A2
0 1 1 W3 = A0 + A1 + A2
1 0 0 W4 = A0 + A1 + A2
1 0 1 W5 = A0 + A1 + A2
1 1 0 W6 = A0 + A1 + A2
1 1 1 W7 = A0 + A1 + A2
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

NOR Row Address Decoder

• For a 3-bit row address decoder, 23=8 NOR gates are required to select the corresponding
word line.
RECALL DYNAMIC LOGIC GATE:

Where is the evaluation NMOS in the decoder circuit?

It is assumed that during the evaluation, all the inputs are 0
(no word line is active); therefore, no need for eval. NMOS
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Exercise 16.12
• How many transistors are needed for a NOR row decoder with an M-bit address?

 How many address lines?

 2M

 How many PMOS per address lines?

 1 per line
 How many NMOS per address line?
 M per line

 How many PMOS total?

 1x2M
 How many NMOS total?
 Mx2M
 How many transistors total?
 (M+1)x2M
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Column Address Decoder

• It connects one of bit lines to the Input/Output line of the chip.
• It is a multiplexer, implemented by pass-transistor logic

NOR decoder (similar to R.A.D)

 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Column Address Decoder

A TREE DECODER: Fewer number of transistor; Slower Circuit
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Column Address Decoder

A TREE DECODER: Fewer number of transistor; Slower Circuit

A2 A1 A0 I/O
0 0 0 I / O = A2 A1 A0 B0
1 I / O = A2 A1 A0 B1
1 0 I / O = A2 A1 A0 B2
1 I / O = A2 A1A0 B3
1 0 0 I / O = A2 A1 A0 B4
1 I / O = A2 A1 A0 B5
1 0 I / O = A2 A1 A0 B6
1 I / O = A2 A1A0 B7
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Exercise 16.13
• How many transistors are needed for a tree decoder with an 2N bit lines?

 How many bit lines?

 2N

 Let’s count from the bottom of the “tree”

 2+2x2+2x2x2+…+2x2x…x2

N-times

 It equals:
 2(1+21+22+…+2N-1)=2(2N-1)
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Pulse-Generation Circuits
1. RING OSCILLATOR
• Odd number of invertors are cascaded & looped around.
• It happened due to propagation delay, tp.
• Provides a method to measure tp.
• For N=(2k+1) invertors cascaded, the pulse period is T=2N.tp and frequency is
f=1/(2Ntp)
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Exercise 16.14
• Find the frequency of oscillation for a ring of five inverters if the inverter
propagation delay is specified to be 1ns.

 f = 1/(2N.tp)
 N=5; tp=1ns  f = 100MHz
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Pulse-Generation Circuits
2. A One-shot or Mono-stable Multi-vibrator circuit
• Even number of invertors are cascaded and inserter as an input to an XOR.
• The other input to XOR is the pre-delay signal
• The single pulse duration, T = N.tp, when N=2k is the number of inverters that are
cascaded.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Read-Only Memory
• ROM is a memory that contains fixed data
Read Only
pattern, e.g. microprocessor basic operating Memory
program.
• It is non-volatile: Preserves data with no power
Programmable
supply. Fixed (ROM)
ROMs
• A ROM is a combinational logic circuit:
o Its inputs are the address of the memory
cells Masked-
PROM
programmable
o Its output are the stored data read on the
bit-line
Erasable
o Therefore, it acts as a Programmable
scrambler/coder/decoder (EPROM)

Flash
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Fixed ROM
• There is an NMOS, fabricated at each cell that
stores a 0.
• No NMOS, at cells that store 1.
• The cell values are fixed through fabrication
process.
• In the case of the ROM in the figure:
o 8 Word x 4 Bit = 32 bit ROM.
o For every word, 4 bits are stored.
o This fixed ROM has a pseudo-NMOS design
 It dissipates static power
 Solution: Using a normally high f control
pulse at the gate of the PMOS and have a
pre-charge (similar to dynamic logic
gates)
 Before each read f is lowered to charge
the bit lines to VDD.
 Then f goes high and the word line is
inserted.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Mask-programmable ROM
1. All the fabrication steps are performed, except the final step of “wiring.”
• A MOS is fabricated at each and every cell.
2. The top of the chip is then coated with a metal, e.g. aluminum
3. Depending on the data intended to be stored in the ROM (per users’ need), a pattern
is transferred to the aluminum using a mask
• The gate of the MOSFETs in the cells storing a 0 are connected to the word line,
otherwise no connection is made.
4. This is done at the final step of fabrication, and provides flexibility and economical
advantage.
5. Note this is a one-time programming, and the resultant ROM is of the fixed type.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Programmable ROMs
• Fuses are incorporated in interconnects.
• The fuses can be selectively blown out by applying large current by the user, e.g.
through applying large emitter current in a BJT.
• This process is irreversible: Programming can only be performed once and in the
first use.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Erasable programmable ROMs

(EPROM)
• An EPROM uses the floating gate MOS transistors.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

EPROM
• A very large gate voltage (~25V), and a very large drain voltage (~16V) are applied.
• This increases the kinetic energy of electrons in the channel, and excites them to
overcome the oxide barrier to reach floating gate and be trapped there.
• In other words, hot electrons are injected to the floating gate from the channel.
• This is a long-lasting state (up to 100 years!) and remains stable without power.
• As a result the I-V of the transistors shift to larger threshold voltages a.k.a
programmed state.
• This is a reversible process: Applying UV light for a long period of time, can restore
the un-programmed state. It is only suitable for infrequent programming.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Flash memories (EEPROM)

• Unlike EPROMs, flash memories are electrically erasable programmable (EEPROM);
• The state of the floating gate transistor can electronically be programmed and
restored.
• It takes much less time compared to erasing the floating gate MOSFET by UV light.
• Rather than UV, tunneling currents are used to charge and discharge the floating
gate.  Oxides should be very thin; fabrication has to be very accurate; requires
advanced technology.
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

CMOS imaging circuits

• An image consists of two-dimensional arrays of pixels.
• An active pixel circuit in CMOS sensor is a unit cell similar to the memory cells in memory
circuits.
• A photodiode D, generates a current proportional to the intensity of light at its location.
• This (photo) current discharges a load capacitor C; The voltage drop DV across C is
proportional to light intensity.
• Each pixel is selected by a Row address, where DV is put on the column.
• This is fed to an analog-to-digital circuit and converted to a digital value for further
processing.