x = 0 x = 1

(a) Two states of a switch

(b) Symbol for a switch

Figure 2.1 A binary switch

 S
Battery x L Light

(a) Simple connection to a battery

S
Power
supply x L

(b) Using a ground connection as the return path

Figure 2.2 A light controlled by a switch

 S S
Power
supply x x L Light
1 2

(a) The logical AND function (series connection)

x
1

Power Light
supply S L

x
2
(b) The logical OR function (parallel connection)

Figure 2.3 Two basic functions

 S

x1 S
Power
supply S x3 L Light

x2

Figure 2.4 A series-parallel connection

 R

Power
supply x S L

Figure 2.5 An inverting circuit

Figure 2.6 A truth table for AND and OR
Figure 2.7 Three-input AND and OR
 x1
x2
x1
x1  x2 x1  x2   xn
x2

xn

(a) AND gates

x1
x2
x1
x1 + x2 x1 + x2 + + xn
x2

xn

(b) OR gates

x x

(c) NOT gate

Figure 2.8 The basic gates
x
1
x
2
f = (x + x )  x
x 1 2 3
3

Figure 2.9 An OR-AND function

 0 01 1 1 10 0
x
1 A
11 0 1
f
0 00 1 B
0 10 1
x
2

(a) Network that implements f = x +x x

1 1 2

x x f (x , x )
1 2 1 2

0 0 1
0 1 1
1 0 0
1 1 1

(b) Truth table for f

Figure 2.10 a Logic network

 1
x
1 0

x 1
2 0

1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram

0 01 1 1 1 0 0
x
1
11 0 1
0 10 1 g
x
2

(d) Network that implements g = x + x

1 2

Figure 2.10 b Logic network

Figure 2.11 Proof of DeMorgan’s theorem
(a) Constant 1 (b) Constant 0

x x x x

(c) Variable x (d) x

x y x y

(e) x  y (f) x + y

x y
x y
z

(g) x  y (h) x  y + z

Figure 2.12 The Venn diagram representation

 x y x y

z z

(a) x (d) x  y

x y x y

z z

(b) y + z (e) x  z

x y x y

z z

(c) x  (y + z ) (f) x  y + x  z

Figure 2.13 Verification of the distributive property

 x y x y

z z

x  y x  y

x y x y

z z

x z x z

x y x y

z z

y  z x  y + x z

x y

x  y + x z+ y  z

Figure 2.14 Verification of x y + xz+ y z= x y+ x z

Figure 2.15 A function to be synthesized
x1
x2

(a) Canonical sum-of-products

x1
f
x2

(b) Minimal-cost realization

Figure 2.16 Two implementations of a function

Figure 2.17 Three-variable Minterms and Maxterms
Figure 2.18 A three-variable function
x2

f
x3
x1

(a) A minimal sum-of-products realization

x1
x3
f

x2

(b) A minimal product-of-sums realization

Figure 2.19 Two realizations of a function

Figure 2.20 Truth table for a three-way light controller
 f

x
1
x
2
x
3

(a) Sum-of-products realization

Figure 2.21 SOP implementation of the three-way light controller

x
3
x
2
x
1

(b) Product-of-sums realization

Figure 2.21 POS implementation of the three-way light controller

 s x1 x2 f (s, x1, x2)
000 0
001 0 x1
010 1
011 1 f
100 0 s
101 1 x2
110 0
111 1

(a)Truth table (b) Circuit

s
s f (s, x1, x2)
x1 0 0 x1
f
x2 1 1 x2

(c) Graphical symbol (d) More compact truth-table representation

Figure 2.22 Multiplexer

Figure 2.23 Screen capture of the Waveform Editor
Figure 2.24 Screen capture of the Graphic Editor
 Design conception

DESIGN ENTRY

Truth table Schematic capture VHDL

Simple synthesis
Translation
(see section 2.8.2)

Merge

INITIAL SYNTHESIS TOOLS Boolean equations

Functional simulation

No
Design correct?

Yes

Logic synthesis, physical design, timing simulation

(see section 4.12)

Figure 2.25 The first stages of a CAD system

 x1
x2
f

x3

Figure 2.26 A simple logic function and corresponding VHDL code

Figure 2.30 VHDL code for a four-input function
x1
x3

x2

x4

Figure 2. 31 Logic circuit for four-input function

 x3
x3

x1 x2 x1 x2

x4 x4

(a) (b)

Figure P2. 1 Two attempts to draw a four-variable Venn diagram

 m0 x4

x1 x2 x

1 x

m2 m1
x3 x

Figure P2. 2 A four-variable Venn diagram

 1
x1
0

x2 1
0

x3 1
0

f 1
0

Time

Figure P2. 3 A timing diagram representing a logic function

 1
x1
0

x2 1
0

x3 1
0

f 1
0

Time

Figure P2. 4 A timing diagram representing a logic function