IBTS Modem Card and Layer 1 and 2 Architecture

iBTS Layer 1 & Layer 2 Architecture
Vikas Dhingra
iBTS Architecture Team
June, 2010
Agenda
iCEM Architecture
xCEM Architecture
eCEM Architecture
bCEM Architecture
2 | Presentation Title | Month 2006 All Rights Reserved © Alcatel-Lucent 2006, #####
Modems
Channel Elements
bCEM
(512)
xCEM eCEM
(256) (256)
iCEM128
CEM
iCEM64
(alpha)
2000 2010
2002 2008 2012
Date of introduction
iCEM Overview/Architecture
Base Band Unit (BBU)
 One CDC (CoDeC) DSP (TI C6416 DSP)
 Three MDM (MoDeM) DSPs (TI C6416 DSPs)
 Three CRCP (Chip Rate Co Processor) ASICs
Hardware Architecture
From the TRM…
FPGA UL data
PDCP Serial
Rach fingers to program the Port
Crcp … To PQ2
HPI
Rach DL ASIC
Detection S Supervision
MDM data CRCP
H
… To PQ2 Serial
A Serial … To PQ2 UL DL
R
Port data data
Port
HPI HPI
E ASIC
CDC Spv D Supervision

MDM Programs CRCP
UL & DL
Utopia
… To PQ2 UL DL
M
Serial
Port data data
E HPI
UL
X
T
E UL
data ASIC
DL
M
M Supervision
MDM CRCP
E
M
FPGA
S DL data
U2TX …To the TRM
BBU architecture
CDC Functions
 UL main functions
– RACH preamble detection and fingers search / AICH
– Soft bits level functions
– TrCH rate dematching
– TrCH de-multiplexing
– De-interleaving
– Viterbi, Turbo decoding
– CRC management
– ATM cells packing, FP transmitter
 DL main functions
– FP receiver
– Coding chain
– CRC attachment
– Transport block concatenation / Code block segmentation
– Channel coding
– Rate matching
– TTI interleaving
 SRLR management
 Compressed mode management
MDM Functions
 UL main functions
– DCH fingers search and demodulation
– RACH message demodulation
– Inner loop power control management
– Soft and Softer HO management
– SRLR management
– Compressed mode management
– Nominal measurements
 DL main functions
– Frame building
– TrCH multiplexing
– Frame interleaving
– TFCI, TPC, Pilot bits and data formatting
– CRCP programming
HSDPA: L1/L2 Impacts Overview
HSUPA – L1/L2 Impacts Overview
Why xCEM ?
αCEM  xCEM is next generation of

BBU Channel Element Module board for
DCH Alcatel-Lucent macro Node-B,
substituting existing iCEM
 R99, HSDPA & HSUPA support provided on
iCEM one module
BBU BBU  Actual capacity increase even more
DCH or HSDPA
DCH
or HSUPA significant with Multi-mode BBU in UA06
 Second form factor available for d-NodeB
2U product
xCEM  xCEM replaces current iCEM module and
is introduced with new ordering code
BBU BBU
DCH DCH  No End Of Life declared on existing iCEM
 Compatible with existing macro iBTS
BBU BBU cabinets and modules
DCH or HSDPA
DCH or HSDPA
or HSUPA
The xCEM Functionality
Functionality
 Enhanced performance & capacity
 256 R99 Channel Elements
 Max. 128 HSPA Channels
 HSDPA 28.8 Mbps shared throughput
 HSUPA 7.7 Mbps decoder throughput
 6 Cells supported (1c6s, 2c3s)
Availability
 Dec 2007 (with UA05.1.1 Load)
xCEM Resource Management
xCEM
64 CE 64 CE 64 CE 64 CE
 256 CE
 up to 128 HSPA connections with
up to 28.8 Mbps shared throughput (DL) and
•HSDPA (128 connections) 7.7 Mbps shared throughput (UL)
 6 cells
•HSUPA (128 connections)
HSPA Connection on xCEM with Multi-mode:
If DCH demodulated on xCEM : If DCH demodulated on iCEM :
• 1(n) CE is consumed out of 4x64 • 1(n) CE is consumed out of 2x64 on iCEM

• 1 HSDPA connection out of 128 • 1 CE is consumed on xCEM
• 1 E-DCH connection out of 128 • 1 HSDPA connection out of 128
• 1 E-DCH connection out of 128
Supported Configurations for a given Carrier
xCEM iCEM αCEM

- R99 R99
- HSDPA R99
- R99 + HSDPA R99 No xCEM
- HSDPA + HSUPA R99
- R99 + HSUPA R99
R99 - -
R99 + HSDPA - - xCEM only
R99 + HSDPA + HSUPA - -
R99 R99 R99
R99 + HSDPA R99 R99
R99 + HSDPA + HSUPA R99 R99
Mixed configurations
R99 HSDPA R99
R99 R99 + HSDPA R99
R99 HSDPA + HSUPA R99
In case of mixed configurations (NodeB equipped with iCEMs & xCEMs):

1. For a given carrier, HSDPA/HSUPA traffic either all on iCEM(s) or all on xCEM(s)
No mixed
In case of NodeB equipped with multiple xCEMs:
1. Max. 2 xCEM boards per NodeB are supported with initial release
2. for HSPA 1 Carrier cannot be distributed across xCEM boards (UA05.1 / UA06)
iCEM vs. xCEM with multimode in UA06
Node-B Processing Capacity for HSPA
iCEM128 iCEM128 iCEM128 xCEM Resource sharing
DCH
•Service DCH – HSDPA – E-DCH
# of CE 64 64 - 256
HSDPA
•Frequency sharing (2 carriers)
# of connections Up to 48 - Up to 48 Up to 128
DL shared Throughput* Up to - Up to Up to •Up to 6 HSPA cells !!

10.8Mbps 10.8Mbps 28.8Mbps
# of cells Up to 3 - Up to 3 Up to 6 Hardware efficiency
# of SF16
3 active cells 7+7+7 - 7+7+7 15 + 15 + 15 •No more HSDPA SF16 code
2 active cells 10 + 10 - 10 + 10 15 + 15 limitation with 3 active cells
1 active cell 15 - 15 15
•High capacity board

# of HS-SCCH Up to 4 - Up to 4 Up to 4
HSUPA i.e. E-DCH 10ms TTI only 10ms TTI only 10 & 2ms TTI
Future proof readiness
# of connections - Up to 15 Up to 15 Up to 128
UL shared throughput** - Up to 2.1 Up to 2.1 Up to 7.7Mbps •2 ms TTI up to 5.7 Mbps

# of cells - Up to 3 Up to 3 Up to 6
•HSPA+
# of E-AGCH - Up to 2 Up to 2 Up to 4
# of E-HICH/E-RGCH - 1 1 Up to 4 •LTE (Up to 20MHz or 2x10MHz DL)

# of signatures - Up to 20 Up to 20 Up to 40
Node-B processing resources dynamically shared over 6 HSPA cells

* MAC-hs throughput
** MAC-e throughput
xCEM Architecture Overview
DSP OneChip ASIC 3

E-DCH TPR OneChip ASIC 2
Compressed OneChip ASIC 1
Calculation OneChip ASIC 0
Mode Tx Bus
Flag generation Rx Bus
CRC check & Rel’99
MAC-e Channel Processing
Flow De- Rate-Matching
multiplexing Parameter UL Chips
Calculation
PQ2 E-DPDCH
Decoding FPGA A
Modem HSDPA Tx Bus
Controller HSDPA Processing
PQ3 FPGA C
MAC-hs schedulers FPGA B HSUPA Tx Bus
MAC-e schedulers Rx Bus
Framing Protocol
HSUPA Processing
HSUPA Processing
XXX
xCEM Board Hardware Architecture
Dual 2 x MMI (optional: 1 GMI) Front

Ethernet Switch 2
Ethernet Panel
MMI
UMTS
OneChip
ASIC
0 New Components
compared with UCU3
MMI Added UCU3
UMTS
OneChip Assets
Ethernet Switch 1
ASIC
1 GMI Added iBTS
Assets
GMI
Combiner FPGA
MMI
UMTS
I/Q UL/DL OneChip
GMI
ASIC
Time 2
iBTS Pulse
HSSL MMI
UMTS
ASIC OneChip
(HSSC) ASIC
3
PCI
HSPA Channel Element
Flash
PowerQUICC3
Local Bus
MPC8555
Utopia ATM BUS ATM PCI
Support
Even Second PowerQUICC2
LEDs
Local Bus MPC8347
MIM CPLD
HSDPA on xCEM
HSUPA on xCEM
OneChip Plus Legacy R99 Mode
OneChip Plus HSDPA Mode
OnceChip Plus EDCH Mode
xCEM OneChipPlus Architecture
OneChip ASIC 3
DSP OneChip ASIC 2 OneChip 3_TX_bus
PQ-III
MII OneChip 2_TX_bus
FPGA OneChip ASIC 1
PCI Interface
Configurations OneChip 1_TX_bus
OneChip ASIC 0
OneChip 0_TX_bus
UMTS TX
UMTS Decoder
MAC-hs & E-DCH TPR
Calculation HSDPA/HSUPA
MAC-e Parameter
ARM
Schedulers Calculation UMTS Decoder UMTS RX & RX_bus
CRC check &
RACH
MAC-e Flow
Demultiplexing
Compress Mode
Flag Generation HS-DPCCH
OC Controller FPGA
E-DPDCH Chip Level
ARM Interface
Decoding Processing
EMIF Interface
EMIF A Bus FPGA A
Interface
ACK/NACK OneChip
Decoding Interface
PCI
Interface
CQI Decoding & Compute
EMIF B Prediction EcI0
DDR Memory
PCI HS-PDSCH HS-PDSCH F-PDCH &
MBMS TX
& HS-SCCH & HS-SCCH HSPDA_TX_bus
EMIF A Encoder Transmitter +
E-DPDCH OneChip
DDR E-DPDCH
2nd Stage Interface
Interface MRC
Despreading
SDR
Memory HSUPA Chip RX_bus
E-DPDCH Rate dematching E-DPCCH E-DPCCH
Level
interleavinghybrid combining Decoding MRC
Processing
E-AGCH, E-RGCH, HSUPA_TX_bus

PCI Interface
E-HICH Transmitter
FPGA B & C
Call Processing Object Model for dedicated and HS channels
eCEM HW Architecture
bCEM/OC-E WCDMA Program
OC-E Feature Set
Performance Enhancements
 Support for 12 cells
 Full implementation of CPC to maximize UE
power savings
 SIR estimation performance enhancements in
support of HSUPA peak throughput
 16QAM HSUPA performance enhancements
 Full implementation of Enhanced F-DPCH
 Full implementation of Enhanced UL Cell FACH
 E-DPCCH RAKE enhancement
 Increase size of OCC ARM TCM memory
Cost Reduction
 40nm technology (<$40 in 2012 vs $54 for OC-CR)
bCEM overview GigE SW
SGMII
Ethernet Maintenance
SGMII to FPGA A (16 ports) port
phy
SGMII to FPGA BC 6 SGMII
GigE port 0_CCM1 (SERDES)


CPU Eth
Flash CPU CPLD debug port
(TBD MB, 16b) phy
DDR3
(1GB, 64b) Mazz con 4 SGMII
soDIMM?
eLB SGMII
DDR3 L2 CPU DSP A
(1GB, 64b) sRIOv1.3
soDIMM? P4080 (4xlane) MSC8156
DDR to
SGMII FPGA B
SGMII sRIO DDR3
(512MB,64b)
sGMII to SW1
GMII bridge DSP B
sRIO
Test port
8-port MSC8156
sRIO port 0 DDR to
sRIO port 1 FPGA B
DDR3
(512MB,64b)
OC-CR- OC-CR-
R8 R8 DSP C
FRONT PANEL
BACKPLANE
PCI-ex
IQ & rake MSC8156
Inter- (2x-lane) DDR to
HSIQ port 0-3 FPGA A FPGA FPGA BC FPGA A
for CCM1 DDR3
V6LX365T V6LX365T (512MB,64b)
Or (use 1156 package)
V6LX240T
HSIQ port 0-3
for CCM2
(for LTE-
3 DDR from
TDD) DSP A,B,C DDR3 DDR3 lack of 3rd DDR3 block excludes for WCDMA
rd
(use 1759 (512MB, 64b) (512MB, 64b) some types of interference cancellation; adding 3
package) memory block adds $60 to the cost
DDR3
(512MB, 64b)
Test pulse port
I2C HSIQ recovered clk
from FPGA A
Presence I2C Clock recovery, Internal cloks
Slot ID
management PLL clean up, sRIO
BP type ID timing gen Test port
1-wire logic,
test jig mode inventory, Remote power
CPLD, Power conversion Part of CPU
on/off
+3.3V MP 1-wire (primary+secondary, CPLD LED
device hot-swap, power
+24V or -48V monitoring)
Functional block color definition
CPU DSP FPGA Switch timing manage OC-CR Power
Note: Not ALL internal interfaces are shown. (eLB, SMI, I2C, clocks, JTAG, alarms, interrupts) are not shown in this level
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IBTS Modem Card and Layer 1 and 2 Architecture

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IBTS Modem Card and Layer 1 and 2 Architecture

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iBTS Layer 1 & Layer 2 Architecture

iBTS Architecture Team

Base Band Unit (BBU)

 One CDC (CoDeC) DSP (TI C6416 DSP)

 Three MDM (MoDeM) DSPs (TI C6416 DSPs)

 Three CRCP (Chip Rate Co Processor) ASICs

CDC Spv D Supervision

αCEM  xCEM is next generation of

HSPA Connection on xCEM with Multi-mode:

If DCH demodulated on xCEM : If DCH demodulated on iCEM :

• 1(n) CE is consumed out of 4x64 • 1(n) CE is consumed out of 2x64 on iCEM

xCEM iCEM αCEM

In case of mixed configurations (NodeB equipped with iCEMs & xCEMs):

DL shared Throughput* Up to - Up to Up to •Up to 6 HSPA cells !!

•High capacity board

UL shared throughput** - Up to 2.1 Up to 2.1 Up to 7.7Mbps •2 ms TTI up to 5.7 Mbps

# of E-HICH/E-RGCH - 1 1 Up to 4 •LTE (Up to 20MHz or 2x10MHz DL)

Node-B processing resources dynamically shared over 6 HSPA cells

DSP OneChip ASIC 3

Dual 2 x MMI (optional: 1 GMI) Front

E-AGCH, E-RGCH, HSUPA_TX_bus

GigE port 0_CCM1 (SERDES)

GigE port 0_CCM2 (SERDES)

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