The ARM Cortex-M3

ARM
 Founded in November 1990
 Spun out of Acorn Computers
 Initial funding from Apple, Acorn and VLSI

 Designs the ARM range of RISC processor cores

 Licenses ARM core designs to semiconductor partners who fabricate and sell
to their customers
 ARM does not fabricate silicon itself

 Also develop technologies to assist with the design-in of the ARM architecture
 Software tools, boards, debug hardware
 Application software
 Bus architectures
 Peripherals, etc
 ARM Cortex Processors
 ARM Cortex-A family (v7-A):
 Applications processors for full OS
and 3rd party applications

 ARM Cortex-R family (v7-R):

 Embedded processors for real-time
signal processing, control applications

 ARM Cortex-M family (v7-M):

 Microcontroller-oriented processors
for MCU and SoC applications
 Data Sizes and Instruction Sets
 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Half-word means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set
 Cortex-M stack Model Main
r0
r1
r2
r3

 Fully programmable in C r4
r5
 Stack-based exception model r6
r7
 Only two processor modes r8
r9
 Thread Mode for User tasks r10
 Handler Mode for OS tasks and exceptions r11
r12
 Vector table contains addresses sp
sp
Process
lr
r15 (pc)

xPSR
 General description

• Operated over low operating frequency

• Low power consumption
• High level of integration
• Operate at CPU frequencies of up to 100 mhz.
• 3-stage pipeline and uses a Harvard architecture
• 512 kb of flash memory, up to 64 kb of data memory
• 8-channel general purpose DMA controller
• 4 UART’s
• 8-channel 12-bit ADC, 10-bit DAC
• 4 general purpose timers
• 70 general purpose I/O pins
• On-chip SRAM
• One motor control PWM
• Watchdog Timer
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down
• Non-mask able Interrupt (NMI) input.
• The Wakeup Interrupt Controller
• Crystal oscillator with an operating range of 1 MHz to 25 MHz
 Data processing Instructions

 Consist of :
 Arithmetic: ADD ADC SUB SBC RSB RSC
 Logical: AND ORR EOR BIC
 Comparisons: CMP CMN TST TEQ
 Data movement: MOV MVN

 These instructions only work on registers, NOT memory.

Block diagram
 Cortex-M3 Pipeline
 Cortex-M3 has 3-stage fetch-decode-execute pipeline
 Similar to ARM7
 Cortex-M3 does more in each stage to increase overall
performance
1st Stage - Fetch 2nd Stage - Decode 3rd Stage - Execute

Address Data Phase

AGU Phase & Write Load/Store &
Back Branch

Instruction
Fetch
Decode & Multiply & Divide Write
(Prefetch)
Register Read

Branch Shift ALU & Branch

Branch forwarding & speculation

Execute stage branch (ALU branch & Load Store Branch)

 Applications
• E-Metering
• Lighting
• Industrial networking
• Alarm systems
• White goods
• Motor control
THANK YOU