A Scalable Physical Model for Nano-Electro

Mechanical Relays
Haider M. Alrudainy ,
1 Dr. Andrey Mokhov ,
2 Prof. Alex Yakovlev 3

School of Electrical and Electronic Engineering, Newcastle University, Newcastle Upon Tyne, GB
1h.m.a.alrudainy@ncl.ac.uk,2andrey.mokhov@ncl.ac.uk,3alex.yakovlev@ncl.ac.uk

 Motivation  Proposed Model:

g g g
Design of scalable and accurate physical model
Cgc
R ch/2 R ch/2 R ch/2 R ch/2 Cgs + Cgd
that can be plugged into the standard EDA
R ch/2 R ch/2
software. f
Ccb Cgb Cgb
 Overcome the simulation convergence problems, Cgs
R pox R pox Cgd Cgs
R pox + R con
R pox + R con Cgd Cgb
due to numerous number of non-linear parasitic + R con + R con R pox + R pox + R con
R trace R trace R con
capacitance and contact discontinuities. d d b s
a b s d s
j b

 (Ccg +Ccb ) ≪ Cgb , (Ccg +Ccb ) ≪ Cgd , (Ccg +Ccb ) ≪ Cgs (Ccg +Ccb ) could be ignored. g
 Needed Switch simulator:  𝑅𝑡𝑟𝑎𝑐𝑒 ≪ 𝑅𝑝𝑜𝑥 , 𝑅𝑡𝑟𝑎𝑐𝑒 ≪ 𝑅𝑐𝑜𝑛 , 𝑅𝑡𝑟𝑎𝑐𝑒 ≪ 𝑅𝑐ℎൗ2 𝑅𝑡𝑟𝑎𝑐𝑒 could be ignored. Cgs + Cgd

 High accuracy.  Linearize the parasitic capacitors (Cgd , Cgs ) added them together.
Cgb
 Fast execution time.  Linearized the parasitic resistor (𝑅𝑐𝑜𝑛 ) then added to 𝑅𝑐ℎൗ2 and 𝑅𝑝𝑜𝑥 .
R pox + R con +
R pox + R con +
d R ch/2
 Tackling the convergence problems. b R ch/2
s

Is highly in demand …..  Results:

 4.6 % latency error rate between the standard and  Model execution time versus clock speed and number of stages.
proposed model
 Suspended Gate Relay:  Increase to less than 7% After cascading of 40  Simulator needs long time to approach the solution at low
AND Gate in series switching frequency.
A2
A1
A0
A1 A10 A40

A0 Simulation Time [n sec.]

A1 A10 A40
Spring-Mass-Damper
Linear Fit
7

K b Model
Measured Error
Error (Latency) [%]
6.5

Gate: 𝐏 + 𝐩𝐨𝐥𝐲 − 𝐒𝐢𝟎.𝟒 𝐆𝐞𝟎.𝟔

6

𝐂𝐠𝐜
Channel Channel
5.5

𝐑 𝐜𝐡/𝟐 𝐂𝐠𝐛 𝐑 𝐜𝐡/𝟐

𝐂𝐠𝐬 𝐂𝐜𝐛 𝐑 𝐩𝐨𝐱 + 𝐑 𝐜𝐨𝐧 𝐂𝐠𝐝
5

𝐑 𝐩𝐨𝐱 + 𝐑 𝐜𝐨𝐧
Base Drain
4 4.5

Insulator : 𝐀𝐥𝟐 𝐎𝟑
Substrate : Si
0 5 10 15 20 25 30 35 40
Fig. 1: NEM Relay Structure Based on [1] Number of stages
Number of stages
 Table below shows the evaluation of the proposed model in terms of latency, scalability, and simulation time.
 Methodology:
 Lumped Verilog-A model based NEMS No. of Latency Simulation Time
 Mechanical dynamics: spring, damper, mass Circuits Relays Std. Pro. Error(%) Std. Pro. Improvement
 Electrical parasitic: capacitor and resistor (%)
Source AND 2 15ns 15.7ns 4.6 3m 4s 2m 23s 23
𝐕𝐒𝐨𝐮𝐫𝐜𝐞 𝟎

𝐅𝐞𝐥𝐞 𝟎 Logic OR 2 15ns 15.6ns 4.0 4m 49s 3m 26s 29

𝐅𝐯𝐝𝐰 𝟎 XOR 2 15ns 15.5ns 3.3 848 ms 783 ms 7
Body

D-Latch 4 15ns 15.7ns 4.6 1m 47s 1m 2s 41

𝒁ሷ
𝒁ሶ

𝐙𝟎
2-input C- 10 15ns 16ns 6.0 6m 28s 3m 55s 39
= −𝒌 − 𝒌𝒎

Lumped electrical parameters4

Sequential element
Lumped mechanical parameters

𝐕𝐒𝐨𝐮𝐫𝐜𝐞 𝟏
𝒎

𝐅𝐞𝐥𝐞 𝟏 3-input C- 14 Div. 17ns ---- Div. 9m 19s ----

Suspended-Gate NEM Relay

𝐅𝐯𝐝𝐰 𝟏 element
𝑸𝒎

1-bit CSA 22 15ns 17ns 13 13m 23s 9m 37s 28

𝟏

𝐙𝟏 1-bit CRA
Verilog-A
Verilog-A
𝒁
𝒁

Arithmetic 12 15ns 16ns 6.0 6m 52s 4m 37s 33

𝟐
𝟏

2-bit CRA 24 Div. 18ns ---- Div. 14m 34s ----

Gate
+

5-bit CRA 60 Div. 22ns ---- Div. 31m 35s ----

𝒎

𝟎
𝟏

5.9 28
𝑭

Average
𝒆𝒍𝒆. + 𝑭𝒗𝒅𝒘

 Conclusion: References:
[1]M. Spencer, F. Chen, et al., "Demonstration of integrated micro-
𝐕𝐒𝐨𝐮𝐫𝐜𝐞

𝐅𝐞𝐥𝐞 𝐍 electro-mechanical relay circuits for VLSI applications," IEEE

Journal of Solid-State Circuits, vol. 46, pp. 308-320, // 2011.
𝐅𝐯𝐝𝐰 𝐍  The new proposed NEM model can be used for simulation a large scale
𝐍

[2] F. K. Chowdhury, D. Saab, and M. Tabib-Azar, "Single-device

design with less than 6 % error rate. "XOR" and "AND" gates for high speed, very low power LSI
𝐅 𝐜𝐨𝐧𝐭𝐚𝐜𝐭

𝐙𝐍 mechanical processors," Sensors and Actuators, A: Physical, // 2012.

 The proposed model can be integrated in the existing EDAs and can be
utilised for better scalability and less execution time than the standard
model.
Contact Contact Follow Publicati

Mechanical Electrica  The methodology of simulating the suspended gate NEM Relay could be us on

adopted to simulate the NEMS in [2].

Drain