MEMORY

SYSTEM LOGICAL MEMORY LAYOUT

• Reserved space of 384KB placed at the top led to

conventional memory barrier due to restriction of conforming
to original memory scheme.
• P IV also ltd by memory map of first PC.
• PC with split personality. Two modes of op different from each
other.
• 286 intro protected mode to access more than 1 MB. But RAM
was non contiguous.
• 386 intro new memory architecture in which only 32 bit
instructions could run. The 4 GB memory capability was only
avail in 32 bit Protected capability.
• OS development delayed.
• All 32 bit CPU are just ‘turbo 386’.
 Problems : 32 CPU

• Distinct memory architecture.

• In real mode for backward compatibility, but only 16 bit
software could run in that mode & access only 1 or 16
MB RAM depending on S/W.
• ROM BIOS & internal drivers are all 16 bit.
• Intel CPU begin op in real mode.
 PROTECTED MODE

• The problem is it is ‘Protected ‘.

• Only dvr pgms are allowed to talk to H/W in this mode. Pgms
loaded by OS are not allowed to access the memory or H/W
directly.
• Diagnostics software
 LAYOUT

• Hardware memory layout is consistent & is independent

of OS.
• Only Memory usage & mgt changes with OS
LOGICAL MEMORY
 Conventional / Base Memory

• In XT DOS could load pgms only in 512 KB called

conventional memory. Remaining reserved for sys use.
• Later changed to 640KB of user memory & 384 KB for
reserved uses creating the 640KB memory barrier.
 UMA

• The reserved 384KB at the top of 1MB.

• First 128KB is reserved for video RAM adapters.
Address rg is A0000 –BFFFF.
• Next 128KB is reserved for ROM on adapter boards.
VGA compatible video adapters use 32 KB. Address rg
from C0000-DFFFF.
• Last 128 KB for M.Bd BIOS. E0000-FFFFF.
• Amt of free UMA varies from system to sys.
• Possible to use the free space for loading 16 bit dvrs &
free the conventional memory.
 VIDEO RAM

• Hold graphics or character info for display. Active only

when in basic VGA mode.
• Modern video card can have 64MB or more on bd
memory , but only 128KB of this avail to the sys in video
RAM area.
 EXTENDED MEMORY

• Memory beyond 1 MB
• Only pgms designed to run in protected mode can make
use of it.
• In 286 pgms designed to run in protected mode.
• 386 or higher sp Virtual Real Mode that op under
Protected mode enabling real mode pgms to execute
under cont of protected mode OS.
 XMS Memory

• Specification developed by MS, Intel & Lotus for pgms to

use extended memory.
• Functions on 286 or higher enabling real mode pgms to
use extended memory
• Before XMS, no way to ensure coop between pgms that
switched CPU into protected mode & used extended
memory since there was no way for one pgm to know
what another pgm was doing with extended memory.
• Extended memory is made to conform to XMS
specification by installing a device dvr in Config.Sys file.
• HIMEM.SYS acts as an arbitrator to pgms that know
XMS protocol.
 ROM

• .
• EPROM
• EEPROM. High voltages reqd during Write & erase op
• Flash Memory a flash cell is based on a single transistor
controlled by trapped charge.
 DRAM

• Refresh rate of 15usec

• Density of 1 billion or
more.
• To store info, T is
turned on & voltage
applied to bit line
causing charge to be
stored in capacitor.
• Even when switched
off, T continues to
conduct & capacitor
discharges due to
leakage resistance
SRAM
 SRAM

• Inverters are X connected to form a latch.

• Latch is connected to two bit lines by transistors
T1 & T2.
• Opened or closed by word line.
• When at grnd level, transistors at grnd level,
transistors are off & latch retains its state.
• Read op – b & b’ complement each other.
Sense/write ccts monitor rhe state of b & b’.
• Write Op – appropriate value placed on b & its
complement on b’ & then word line is activated.
The reqd sig are generated by sense/Write cct
 CMOS CELL

• Transistor pairs (T3, T5) & (T4,T6) form inverters in the latch
 Cache

• Access times are 2ns or lower & thus able to keep up

with CPU.
• No refreshing.
• 30 times larger & 30 times more expensive.
• Not reqd in sys at 16MHz or lower.
• Effectiveness – ‘Hit Ratio’
• When cache controller fails to preload desired data –
‘Cache Miss’
• 3 GHz CPU with integral cache would be op at speeds of
0.33ns but when it has to read from 400MHz memory it
slows down by 7.5 times or 2.5ns using wait states.
• Cache appeared in 386 when CPU crossed 20 MHZ
barrier.
• 486 had integral cache.
• L2 cache
– On M.bd
– Inside CPU die
• Itanium has 3 level cache.
• Cache controller – inside chipset/CPU
– Dictates cache performance & capabilities.
– Limit on amt of memory that can be cached.
– Pentium CPU’s 430 series can cache only 64 MB
– PII can address up to 64Gb but cache only 512MB.
R/W
CS
 Internal Org of Memory Chips

• Memory cells are org in form of an array, with each cell

capable of storing one bit.
• Each row constitutes a word, & all cells of a row are
connected to a common ‘word line’, driven by decoder.
• Cells in each coln are connected to a Sense/Write cct by
two bit lines.
• Sense/Write cct are connected to data I/O lines of chip.
• Tx/Rx info depending on whtehr Rd or Write op.
• Latency Time reqd to perform first access.
• Burst Mode Four consecutive chunks of 64 bits read
thereby lowering the overhead.
• Interleaving Increases bandwidth by dividing memory in
to multiple blocks .
• Speed Rating
– Asynch SDRAM rated in terms of nano sec.
– SDRAM ratings in terms of freq
– Memory rated slightly higher preferred.
– To avoid confusion Intel has created a specification for SDRAM.
PC100 modules are generally rated at 8ns
 DRAM TECHNOLOGIES

• Conventional DRAM
• FPM DRAM.
Sends row address once for multiple accesses.
Allows burst timing of 5-3-3-3
Not suited for buses over 66MHz
 EDO

• Hyper Page Mode DRAM.

• Slightly faster as one access to memory can begin
before last one has finished.
• 3-5% faster.
• Allows burst timings of 5-2-2-2 at 66MHZ.
• BEDO
Higher bus speeds
Sys timings of 5-1-1-1
competes with SDRAM in terms of performance
 SDRAM

• IN synch with memory bus.

• Since DRAM, initial latency same
• Burst access 5-1-1-1.
• Capable of supporting up to 133MHZ.
• SPD
• DDR SDRAM
– 184 pin DIMM
– Clk speed from 1000\ MHz to 400MHz
– Sp dual channel at 800MHZ FSB,
– 64 bits at a time with each channel transferring 3200 MBps
– 2.5V
 DDR2 SDRAM

• Use modified signaling scheme for higher rates & is still

double data rate.
• Starts at 400MHz & is expected to reach 800MHz.
• 1.8V
 RDRAM

• Narrow channel sys against Wide Channel. Similar to

evolving buses.
• 16 bit channel at 800Mhz.
• Dual channel
• Newer versions at 1066, 1200 MHz 16 bit, 32 /64 bit
multi channel giving 9.6GBps per
• Low voltage
MEMORY PACKAGING
 DIP
• Rectangular ceramic pkg
with pins along longer
edge.
• Directly soldered.
• Chip creep.
• Upgrading & trouble
shooting
 Memory Modules

• DIP not used directly.

• DIPs are soldered on to small cct bds called memory
modules
• SIMM
• DIMM
SIMM
• 30 pin SIMM module was designed for 8-bit data
flow, and are generally placed in groups of four
to give a 32-bit data path. 32 bit operation would
be 4, 30 pin SIMM's at a time.
• Thus the 72 pin SIMM was designed for 32-bit
operation, reducing the number of sockets
required although this had to be off-set with a
50% increase in physical length.
 DIMM

• To handle 64-bit operation the 72 pin SIMM

would need to 'pair-up', causing a space
problem.
• DIMM module uses both sides of the chip with
168 pin version having 84 pins on each side.
Each pin is completely independent of the
others, and makes a separate electrical contact.
The density of the DIMM memory module is
increased with only the slightest increase in the
module’s physical size.
DIMM
 DIMM

• Choice for newer memory tech.

• Come in two different voltages – 3.3 or 5V.
• Smaller version for laptop
• 168 pin module for SDRAM
• 184 pin for DDR SDRAM
 Gold & Tin Connectors & Sockets

• Always use gold modules in gold sockets & tin modules

in tin sockets.
• DIMM generally comes with gold connectors.
 Memory Banks & Package Bit Width

• Bank qty of memory wide enough to match the width of

the data bus
• Arrange memory so that full data bus width is transferred
in one cycle.
• Partial bank of memory is not read
• Memory pkg must be matched with data bus
 Memory Size specification

• DxW–S
• D – depth of module in millions/ mega bit
• W – width of module in bits.
• S – in nano sec.
• 2x32-60
• 4x64 -7.5
 QUALITY FACTORS

• DRAM Qlty
• No of chips on module
• Module Qlty
• Warranty
 Memory Errors

• Hard Errors
– Repeatable
– Consistently incorrect results
– Physical problems
 Memory Errors

• Soft Errors
– Transient
– Physically bad memory
– Difficult to diagnose